Abstract: A sensing structure is presented for use in testing integrated circuits on a substrate. The sensing structure includes a probe region corresponding to a conductive region for connecting to the integrated circuit. A first sensing region at least partially surrounds the probe region. A plurality of sensing elements connects in series such that a first of the plurality of sensing elements has two terminals respectively connected to the first sensing region and the probe region. And a second of the plurality of sensing elements has two terminals respectively connected to the probe region and a first reference potential.

Abstract: A device includes a touch and pressure sensitive screen having touch pressure sensors and a controller. The controller acquires touch pressure data from the plurality of touch pressure sensors. For each touch pressure sensor, the controller determines whether the touch pressure data from that touch pressure sensor is indicative of abnormal operation of that touch pressure sensor. Where no abnormal operation is indicated, the controller sums the touch pressure data from each of the touch pressure sensors to produce a touch pressure output. Where abnormal operation is indicated, the controller sums the touch pressure data from each of the touch pressure sensors and multiply the sum by a correction factor to produce the touch pressure output.

Abstract: A channel stream is received and demultiplexed into a video packetized elementary stream (PES), audio packetized elementary stream (PES), and program clock reference (PCR). Indexing circuitry stores the video PES and the audio PES in a buffer, locates a presentation time stamp (PTS) in the video PES and stores that PTS in the buffer, locates a start of each group of pictures (GOP) in the video PES and stores those locations in the buffer, and locates a PTS in the audio PES and stores that PTS in the buffer. Control circuitry empties the buffer of an oldest GOP in the video PES if the PCR is greater than the PTS of a second oldest GOP stored in the buffer, and empties the buffer of each PES packet of the audio PES that has a PTS that is less than the PTS of the oldest GOP stored.

Abstract: The mirror group is formed by a monolithic frame bent along a bending line and including a first and a second supporting portions carrying, respectively, a first and a second chips forming two micromirrors made using MEMS technology. The first and second supporting portions are arranged on opposite sides of the bending line of the frame, angularly inclined with respect to each other. The mirror group is obtained by separating a shaped metal tape carrying a plurality of frames, having flexible electric connection elements. After attaching the chips, the frames are precut, bent along the bending line, and separated.

Abstract: Disclosed herein is a touch screen controller operable with a touch screen having force lines and sense lines. The touch screen controller includes drive circuitry driving the force lines with a force signal in a touch data sensing mode and not driving the force lines in a noise sensing mode. Sense circuitry senses data at the sense lines in the touch data sensing mode and the noise sensing mode. Processing circuitry samples the data, multiplies the data by a sine multiplier to produce imaginary data, sums the imaginary data, multiplies the data by a cosine multiplier to produce real data, sums the real data, and determines magnitude values of the data as a function of the imaginary data and the real data.

Abstract: A device voltage shifter includes a first voltage reference node, a second voltage reference node, an output node and a clamp node. A first high-voltage switching transistor of the voltage shifter has a first conduction terminal coupled to the first voltage reference node and a second conduction terminal coupled to the clamp node. A second high-voltage switching transistor of the voltage shifter has a first conduction terminal coupled to the clamp node and a second conduction terminal coupled to the second voltage reference node. A third high-voltage switching transistor of the voltage shifter has a first conduction terminal coupled to the first voltage reference node, a control terminal coupled to the clamp node, and a second conduction terminal coupled to the output node. A voltage regulator of the voltage shifter is coupled between the output node and the clamp node.

Abstract: An integrated circuit includes a power supply terminal, a reference terminal, and a signal terminal. A first protection device is coupled between the signal terminal and the power supply terminal, the first protection device including a first MOS transistor. A second protection device is coupled between the signal terminal and the reference terminal, the second protection device including a second MOS transistor. Gates of the MOS transistors are directly or indirectly coupled to the reference terminal. Substrates of the MOS transistors are coupled to the reference terminal via a common resistor.

Abstract: A method for co-integrating finFETs of two semiconductor material types, e.g., Si and SiGe, on a bulk substrate is described. Fins for finFETs may be formed in an epitaxial layer of a first semiconductor type, and covered with an insulator. A portion of the fins may be removed to form voids in the insulator, and the voids may be filled by epitaxially growing a semiconductor material of a second type in the voids. The co-integrated finFETs may be formed at a same device level.

Abstract: A light projection system includes a light module emitting a light beam and a movable mirror reflecting the light beam toward a surface. A graphics processing unit processes video data to compensate for a response of the light module. The response is an optical power of the light beam produced by the light module for a given forward current through the light module. A light source driver controls the light module as a function of the processed video data. Colors of the images from the video data produced on the surface by the light beam would otherwise not look as they are intended to look due to changing of the response of the light module, but the processing of the video data alters the video data such that the colors of the images from the video data produced on the surface look as they are intended to look.

Abstract: A circuit includes a first transistor and a second transistor having respective control terminals coupled to receive first and second bias voltages. A first electronic switch is coupled in series with, and between current paths of the first and second transistors to provide an output current line between a circuit output node and ground. A second electronic switch is selectively activated to a conductive state in order to provide a charge transfer current path between a bias node and a charge transfer node in the output current line. A third electronic switch is selectively activated to a conductive state in order to provide a charge transfer current path between the charge transfer node and the control terminal of the second transistor.

Abstract: A microelectromechanical device includes a body of semiconductor material, which forms a cavity, a mobile structure, and an actuation structure. The actuation structure includes at least one first deformable element which faces the cavity and is mechanically coupled to the body and to the mobile structure, and a piezoelectric-actuation system which can be controlled so as to deform the first deformable element and cause a consequent rotation of the mobile structure. The mobile structure includes a supporting region and at least one first pillar region, the first pillar region being mechanically coupled to the first deformable element, the supporting region being set on the first pillar region and overlying at least part of the first deformable element.

Abstract: An encapsulated device of semiconductor material wherein a chip of semiconductor material is fixed to a base element of a packaging body through at least one pillar element having elasticity and deformability greater than the chip, for example a Young's modulus lower than 300 MPa. In one example, four pillar elements are fixed in proximity of the corners of a fixing surface of the chip and operate as uncoupling structure, which prevents transfer of stresses and deformations of the base element to the chip.

Abstract: The present disclosure is directed to a method and system for compensating mismatches among sub-converters in a time interleaved analog digital converter structure. A digital finite impulse response (FIR) equalization filtering unit is coupled to outputs of the sub-converters. The FIR filtering unit includes a digital FIR filter dedicated to each sub-converter. The FIR filtering coefficient is adapted specifically for each sub-converter to achieve a compensation for sub-converter mismatches and inter-symbol interference (ISI) equalization.

Abstract: Embodiments of the circuits described include a method wherein at least one command signal is activated. The activation of the at least one command signal causes a request to a testing circuit of a memory array to enter a memory test mode. The requested memory test mode permits at least part of the memory array to be read. In response to activation of the at least one command signal, a test control circuit initiates an overwrite sequence to overwrite the data stored in the memory array. The test control circuit enables the memory test mode once the overwrite sequence has been completed.

Abstract: A method of manufacturing first, second, and third transistors of different types inside and on top of first, second, and third semiconductor areas of an integrated circuit, including the steps of: a) depositing a first dielectric layer and a first polysilicon layer on the third areas; b) depositing a second dielectric layer on the second areas; c) depositing an interface layer on the first areas; d) depositing a layer of a material of high permittivity and then a layer of a metallic material on the first and second areas; e) depositing a second polysilicon layer on the first, second, and third areas; f) defining the gates of the transistors in the third areas; and g) defining the gates of the transistors in the first and second areas.

Abstract: A building structure includes a block of building material and a magnetic circuit buried in the block of building material. The structure also includes a plurality of sensing devices buried in the block of building material. Each sensing device may include a contactless power supplying circuit magnetically coupled with the magnetic circuit to generate a supply voltage when the magnetic circuit is subject to a variable magnetic field.

Abstract: An embodiment device includes an optical source configured to generate an optical carrier including an optical pulse train; and a modulator configured to modulate an amplitude of the optical pulse train, based on data generated by a data source, to produce a modulated optical signal.

Abstract: A method determines a movement of an apparatus between capturing first and second images. The method includes testing model hypotheses of the movement by for example a RANSAC algorithm, operating on a set of first points in the first image and assumed corresponding second points in the second image to deliver the best model hypothesis. The testing includes, for each first point, calculating a corresponding estimated point using the tested model hypothesis, determining the back-projection error between the estimated point and the second point in the second image, and comparing each back projection error with a threshold. The testing comprises for each first point, determining a correction term based on an estimation of the depth of the first point in the first image and an estimation of the movement between the first and second images, and determining the threshold associated with the first point by using said correction term.

Abstract: A charge pump includes boosting circuits cascade coupled between first and second nodes, wherein each boosting circuit is operable in both a positive voltage boosting mode to positively boost voltage and a negative voltage boosting mode to negatively boost voltage. A first switching circuit selectively applies a first voltage to one of the cascaded boosting circuits in response to a first logic state of a periodic enable signal, with the cascaded boosting circuits operating in the positive voltage boosting mode to produce a high positive voltage at the second node. A second switching circuit selectively applies a second voltage to another of the cascaded boosting circuits in response to a second logic state of the periodic enable signal, with the cascaded boosting circuits operating in the negative voltage boosting mode to produce a high negative voltage at the first node. Simultaneous output of the positive and negative voltages is made.

Abstract: A device includes an array of single photon avalanche diodes (SPADs) and a plurality of pulse shapers. Each of the SPADs are electrically coupled to a respective SPAD quench circuit. Each of the pulse shapers have an input electrically coupled to an output of a respective SPAD quench circuit.