Abstract: Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

Abstract: A strip of sacrificial semiconductor material is formed on top of a non-sacrificial semiconductor material substrate layer. A conformal layer of the non-sacrificial semiconductor material is epitaxially grown to cover the substrate layer and the strip of sacrificial semiconductor material. An etch is performed to selectively remove the strip of sacrificial semiconductor material and leave a hollow channel surrounded by the conformal layer and the substrate layer. Using an anneal, the conformal layer and the substrate layer are reflowed to produce an optical waveguide structure including the hollow channel.

Abstract: A transducer includes a first substrate and an integrated circuit coupled to the first substrate. A sensor is electrically coupled to the integrated circuit and includes a second substrate having a first surface and a second surface opposite the first surface. The second substrate has scribe boundaries defining an outer edge of the second substrate and a chamber extending from the first surface towards but not reaching the second surface. A chamber extends from the second surface to meet the chamber from first surface. Scribe trenches in the second surface at the scribe boundaries have a width from the scribe boundary towards the chamber extending from the second surface. A membrane extends over the first surface and over the chamber extending from first surface. A plate extends from the first surface of the second substrate over the membrane.

Abstract: A device disclosed herein includes a feedback measuring circuit to measure a signal flowing through a movable MEMS mirror. Processing circuitry determines a time at which the signal indicates that a capacitance of the movable MEMS mirror is substantially at a maximum capacitance. The processing circuitry also determines, over a window of time extending from the time at which the signal indicates that the capacitance of the movable MEMS mirror is substantially at the maximum to a given time, a total change in capacitance of the movable MEMS mirror compared to the maximum capacitance. The processor further determines the capacitance at the given time as a function of the total change in capacitance, and determines an opening angle of the movable MEMS mirror as a function of the capacitance at the given time.

Abstract: An electronic device for providing ESD protection is formed by a MOS transistor. the MOS transistor includes a source region and a drain region that are separated from each other by a channel-forming region. A first gate is located over the channel forming region. The drain region includes an extension region. A second gate is located over the extension region. The first and second gates are electrically connected to each other.

Abstract: An imaging cell includes a skimming gate transistor coupled between a photosensitive charge node and an intermediate node and a transfer gate transistor coupled between the intermediate node and a sense node. The skimming gate transistor includes a vertical gate electrode structure formed by a first capacitive deep trench isolation extending into a substrate and a second capacitive deep trench isolation extending into the substrate. A channel of the skimming gate transistor is positioned between the first and second capacitive deep trench isolations. Each capacitive deep trench isolation is formed by a trench that is lined with an insulating liner and filled with a conductive or semiconductive material.

Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.

Abstract: A method for writing a set of information for processing by a processing unit of an integrated circuit in an external memory outside the integrated circuit, includes: generating, within the integrated circuit, an encryption key; for each item of information intended to be written at an address of the external memory, first encrypting the address within the integrated circuit by a first encryption/decryption circuit using the encryption key to obtain an encrypted address; second encrypting the item of information within the integrated circuit using a second encryption/decryption circuit using the encrypted address to obtain an encrypted item of information; and writing the encrypted item of information at the address of the external memory, wherein the external memory is not able to be written twice at a same address during a write process

Abstract: A smart button for use in a network formed on a garment includes a housing and an antenna carried within the housing to communicate with elements of the network. A functional element is carried within the housing. An electronic circuit is carried within the housing and coupled to the antenna and the at least one functional element. The housing is formed by a stem carrying a head, and the antenna is housed within the head.

Abstract: A LED driving circuit includes a power factor correction circuit receiving a rectified mains voltage and providing output to a DC voltage bus, a string of LEDs connected in series, a voltage converter receiving input from the DC voltage bus and providing output to the string of LEDs, and a microcontroller. The microcontroller receives a plurality of digital feedback signals from the voltage converter, controls the voltage converter based upon a user desired brightness level and the plurality of digital feedback signals, and receive a plurality of feedback signals from the power factor correction circuit. Based on the plurality of feedback signals, the microcontroller operates the power factor correction circuit in transition mode where the user desired brightness level is above a threshold brightness, and operates the power factor correction circuit in discontinuous mode where the user desired brightness level is below the threshold brightness.

Abstract: A fin field effect transistor includes a Si fin including a central portion between end portions of the fin, and a SiGe channel region disposed on the central portion of the fin. The SiGe channel region includes a facet free SiGe region having Ge atoms diffused into the Si fin and includes a same shape as the Si fin outside the central portion.

Abstract: Each pixel of a global shutter back-side illuminated image sensor includes a photosensitive area. On a front surface, a first transistor includes a vertical ring-shaped electrode penetrating into the photosensitive area and laterally delimiting a memory area. The memory area penetrates into the photosensitive area less deeply than the insulated vertical ring-shaped electrode. A read area is formed in an intermediate area which is formed in the memory area. The memory area, the intermediate area and read area define a second transistor having an insulated horizontal electrode forming a gate of the second transistor. The memory area may be formed by a first and second memory areas and an output signal is generated indicative of a difference between charge stored in the first memory area and charge stored in the second memory area after a charge transfer to the first memory area.

Abstract: An EEPROM memory cell includes a dual-gate MOS transistor in which the two gates are separated by an insulation layer. The insulation layer includes a first portion and a second portion having lower insulation properties than the first one. The second portion is located at least partially above a channel region of the transistor.

Abstract: A radiation-hard electronic device including a package structure, a semiconductor chip in a cavity within the package structure, an integrated circuit in the semiconductor chip, and structures for protection from radiation for protecting the integrated circuit from ionizing radiation. The structures for protection from radiation include a protective layer of gel, which occupies at least in part the cavity and coats the semiconductor chip.

Abstract: The electrode for a structure of Metal-Insulator-Metal type is formed by a stack successively comprising a gold layer, a barrier layer made from electrically conducting oxide and a platinum layer. The electrically conducting oxide is advantageously a noble metal oxide, and preferentially ruthenium oxide. The electrode is arranged on a substrate. The gold layer of the electrode is separated from the substrate by an adhesion layer made from titanium dioxide. The electrode is used to fabricate a capacitor of Metal-Insulator-Metal type.

Abstract: A plurality of metal tracks are formed in a plurality of intermetal dielectric layers stacked in an integrated circuit die. Thin protective dielectric layers are formed around the metal tracks. The protective dielectric layers act as a hard mask to define contact vias between metal tracks in the intermetal dielectric layers.

Abstract: A oxide-based direct-access resistive nonvolatile memory may include within the interconnect portion of the integrated circuit a memory plane including capacitive memory cells extending in orthogonal first and second directions and each including a first electrode, a dielectric region and a second electrode. The memory plane may include conductive pads of square or rectangular shape forming the first electrodes. The stack of the dielectric layer and the second conductive layer covers the pads in the first direction and forms, in the second direction, conductive bands extending over and between the pads. The second electrodes may be formed by zones of the second bands facing the pads.

Abstract: A semiconductor-based multi-sensor module integrates miniature temperature, pressure, and humidity sensors onto a single substrate. Pressure and humidity sensors can be implemented as capacitive thin film sensors, while the temperature sensor is implemented as a precision miniature Wheatstone bridge. Such multi-sensor modules can be used as building blocks in application-specific integrated circuits (ASICs). Furthermore, the multi-sensor module can be built on top of existing circuitry that can be used to process signals from the sensors. An integrated multi-sensor module that uses differential sensors can measure a variety of localized ambient environmental conditions substantially simultaneously, and with a high level of precision. The multi-sensor module also features an integrated heater that can be used to calibrate or to adjust the sensors, either automatically or as needed.

Abstract: A positioning apparatus includes: a reference device configured to provide a measured current motion angle of a vehicle; an inertial sensor configured to provide a current input angular rate of the vehicle and associated with at least one inertial sensor behavior parameter dependent on inertial sensor temperature; a temperature sensor configured to provide an input temperature variation of the inertial sensor on a time interval; and a digital estimator configured to recursively computing an estimated current motion angle of the vehicle and at least one previously estimated inertial sensor behavior parameter as function of: the measured current motion angle, a previously estimated motion angle, the current input angular rate, and the input temperature variation.

Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.