Abstract: A system includes a multi-conductor bus, a master device coupled to the multi-conductor bus, and at least one slave device coupled to the multi-conductor bus. The multi-conductor bus has a clock line and a data line. The master device is arranged to transmit an address configuration sequence, and the at least one slave device is arranged to configurably determine its own address based on at least one portion of the address configuration sequence. The at least one slave device has a physical address configuration input coupled to either a fixed voltage potential or a changing voltage potential. The at least one slave device is arranged with a first address during a pre-initialization state and arranged with a second address during a post-initialization state.

Abstract: A process for manufacturing an integrated semiconductor device, envisages: forming a MEMS structure; forming an ASIC electronic circuit; and electrically coupling the MEMS structure to the ASIC electronic circuit. The MEMS structure and the ASIC electronic circuit are integrated starting from a same substrate including semiconductor material; wherein the MEMS structure is formed at a first surface of the substrate, and the ASIC electronic circuit is formed at a second surface of the substrate, vertically opposite to the first surface in a direction transverse to a horizontal plane of extension of the first surface and of the second surface.

Abstract: An array of Geiger-mode avalanche photodiodes is formed in a die and includes: an internal dielectric structure, arranged on the die; and an external dielectric region arranged on the internal dielectric structure. The external dielectric region is formed by an external material that absorbs radiation having a wavelength that falls in a stop-band with low wavelength and transmits radiation having a wavelength that falls in a pass-band with high wavelength, at least part of the pass-band including wavelengths in the infrared. The internal dielectric structure is formed by one or more internal materials that substantially transmit radiation having a wavelength that falls in the stop-band and in the pass-band and have refractive indices that fall in an interval having an amplitude of 0.4. In the stop-band and in the pass-band the external dielectric region has a refractive index with the real part that falls in the above interval.

Abstract: According to principles as taught herein, a leadframe array for a semiconductor die is prepared having locations to receive solder balls. Solder balls are then applied to the leadframe array, after which the leadframe array and solder ball combination is placed in a first mold and encased in a first molding compound. After the molding compound is cured, a layer of molding compound is removed to expose the solder balls. After this, a semiconductor die is electrically connected to the exposed solder balls. The combined semiconductor die and leadframe are placed in a second mold, and a second molding compound injected. The second molding compound flows around the semiconductor die and leadframe combination, fully enclosing the electrical connections between the leadframe and the semiconductor die, making the final package a twice-molded configuration. After this, the twice-molded semiconductor package array is cut at the appropriate locations to singulate the packages into individual products.

Abstract: An analog video signal supply circuit includes a processing circuit that supplies first and second digital video signals. First and second digital-to-analog converters convert digital signals to analog signals. A control circuit controls operation in a first configuration where the first digital video signal is applied to an input of the first digital-to-analog converter and the second digital video signal to an input of the second digital-to-analog converter. The control circuit further controls operation in a second configuration where the first digital video signal is simultaneously applied to the inputs of the first and second digital-to-analog converters.

Abstract: A method and controller for controlling a converter are provided. The converter is operated in a first phase in which controller logic asserts a first gate drive signal to cause a first transistor of the converter to be conductive and deasserts a second gate drive signal to cause a second transistor of the converter to be non-conductive. In a first deadtime phase and a second phase, the controller logic deasserts both the first and second gate drive signals to cause leakage energy from a leakage inductance of a primary winding of the converter to be transferred to a clamp capacitance of the converter. After the leakage energy is transferred, the converter is operated in a third phase in which the logic asserts the second gate drive signal and deasserts the first gate drive signal.

Abstract: A voltage generator circuit uses a feedback loop to regulate an output voltage at an output node. A pair of opposite conductivity source-follower transistors are coupled to the output node. A first one of the source-follower transistors operates to provide a fast current transient for charging a capacitive load that is switchably connected to the output node. A second one of the source-follower transistor operate under feedback control to regulate the voltage level at the output node.

Abstract: An integrated electronic circuit includes a semiconductor substrate with a semiconductor well that is isolated by a buried semiconductor region located under the semiconductor well. A vertical MOS transistor formed in the semiconductor well includes a source-drain region provided by the buried semiconductor region. Backside thinning of the semiconductor substrate is detected by biasing the vertical MOS transistor into an on condition to supply a current and then comparing that current to a threshold. Current less than a threshold is indicative that the semiconductor substrate has been thinned from the backside.

Abstract: A rectifying element includes a MOS transistor series-connected with a Schottky diode. A bias voltage is applied between the control terminal of the MOS transistor and the terminal of the Schottky diode opposite to the transistor. A pair of the rectifying elements are substituted for diodes of a rectifying bridge circuit. Alternatively, the control terminal bias is supplied from a cross-coupling against the Schottky diodes. In another implementation, the Schottky diodes are omitted and the bias voltage applied to control terminals of the MOS transistors is switched in response to cross-coupled divided source-drain voltages of the MOS transistors. The circuits form components of a power converter.

Abstract: A one-way switch has a gate referenced to a main back side electrode. An N-type substrate includes a P-type anode layer covering a back side and a surrounding P-type wall. First and second P-type wells are formed on the front side of the N-type substrate. An N-type cathode region is located in the first P-type well. An N-type gate region is located in the second P-type well. A gate metallization covers both the N-type gate region and a portion of the second P-type well. The second P-type well is separated from the P-type wall by the N-type substrate except at a location of a P-type strip that is formed in the N-type substrate and connects a portion on one side of the second P-type well to an upper portion of said P-type wall.

Abstract: A micro-electro-mechanical (MEMS) device is formed in a first wafer overlying and bonded to a second wafer. The first wafer includes a fixed part, a movable part, and elastic elements that elastically couple the movable part and the fixed part. The movable part further carries actuation elements configured to control a relative movement, such as a rotation, of the movable part with respect to the fixed part. The second wafer is bonded to the first wafer through projections extending from the first wafer. The projections may, for example, be formed by selectively removing part of a semiconductor layer. A composite wafer formed by the first and second wafers is cut to form many MEMS devices.

Abstract: Disclosed herein is a test apparatus for a device under test. The test apparatus includes a voltage translator coupled to receive test data from the device under test, over a physical interface, using one of a plurality of I/O standards, with the voltage translator being capable of communication using each of the plurality of I/O standards. A programmable interface is configured to receive the test data from the voltage translator. A bit error rate determination circuit is configured to receive the test data from the programmable interface and to determine a bit error rate of reception of the test data over the physical interface based upon a comparison of the test data to check data.

Abstract: A MEMS device includes a fixed supporting body forming a cavity, a mobile element suspended over the cavity, and an elastic element arranged between the fixed supporting body and the mobile element. First, second, third, and fourth piezoelectric elements are mechanically coupled to the elastic element, which has a shape symmetrical with respect to a direction. The first and second piezoelectric elements are arranged symmetrically with respect to the third and fourth piezoelectric elements, respectively. The first and fourth piezoelectric elements are configured to receive a first control signal, whereas the second and third piezoelectric elements are configured to receive a second control signal, which is in phase opposition with respect to the first control signal so that the first, second, third, and fourth piezoelectric elements deform the elastic element, with consequent rotation of the mobile element about the direction.

Abstract: A color image sensor including an array of pixels is formed in a semiconductor layer having a back side that receives an illumination. Insulated conductive walls penetrate into the semiconductor layer from the back side and separate the pixels from one another. For each pixel, a color pixel penetrates into from 5 to 30% of a thickness of the semiconductor layer from the back side and occupies at least 90% of the surface area delimited by the walls. An electrically-conductive layer extends from the lateral wall of the filter all the way to the walls.

Abstract: Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.

Abstract: A method of manufacturing an electronic device for providing galvanic isolation includes forming a dielectric layer on a semiconductor body and integrating, in the dielectric layer, a galvanic isolation module, the integrating including forming a first metal region at a first height of the dielectric layer. A second metal region is formed at a second height greater than the first height of the dielectric layer, the first and second metal regions being at least one of capacitively and magnetically coupleable together. Forming the second metal region includes etching selective portions of the dielectric layer to form at least one trench having a side wall coupled to a bottom wall through rounded surface portions, and filling each trench with metal material to form the second metal region having rounded edges.

Abstract: An electronic device randomly modifies a current profile of a logic circuit by using an auxiliary circuit. The logic circuit includes a first terminal coupled to a supply voltage terminal, a second terminal coupled to a reference voltage terminal and an output terminal configured to deliver a signal in a high state or a low state. The auxiliary circuit is coupled between the first terminal and the second terminal and is configured to randomly generate or not generate an additional current between the first terminal and the second terminal on each change of state of the signal on the output terminal.

Abstract: A microfluidic valve includes: a first structural layer and a second structural layer; a microfluidic circuit having a first microfluidic conduit and a second microfluidic conduit, which are defined in a superficial portion of the first structural layer, are adjacent, and are separated by a wall; a membrane set between the first structural layer and the second structural layer and delimiting the microfluidic circuit on one side; and a recess containing a gaseous fluid in the second structural layer. The membrane is movable in response to an actuation stimulus between a closed position, in which the first and second microfluidic conduits are fluidly decoupled, and an open position, in which the membrane is at least in part retracted into the recess and the first and second microfluidic conduits are fluidly coupled by means of a fluidic passage defined between the wall and the membrane.

Abstract: A process for manufacturing an interaction system of a microelectromechanical type for a storage medium, the interaction system provided with a supporting element and an interaction element carried by the supporting element, envisages the steps of: providing a wafer of semiconductor material having a substrate with a first type of conductivity (P) and a top surface; forming a first interaction region having a second type of conductivity (N), opposite to the first type of conductivity (P), in a surface portion of the substrate in the proximity of the top surface; and carrying out an electrochemical etch of the substrate starting from the top surface, the etching being selective with respect to the second type of conductivity (N), so as to remove the surface portion of the substrate and separate the first interaction region from the substrate, thus forming the supporting element.

Abstract: A method is to detect a message compatible with the OTA (Over The Air) standard and affected by a wrong ciphering. The method may include receiving the ciphered OTA message; deciphering the OTA message; and reading a counter field of padding bytes in the deciphered OTA message and reading corresponding padding bytes in the OTA message deciphered. The method may also include detecting at least one bit in at least one of the padding bytes of the OTA message deciphered, with the at least one bit being indicative of the wrong ciphering.