Abstract: A MEMS device includes a fixed structure and a mobile structure with a reflecting element coupled to the fixed structure through at least a first deformable structure and a second deformable structure. Each of the first and second deformable structures includes a respective number of main piezoelectric elements, with the main piezoelectric elements of the first and second deformable structures configured to be electrically controlled for causing oscillations of the mobile structure about a first axis and a second axis, respectively. The first deformable structure further includes a respective number of secondary piezoelectric elements configured to be controlled so as to vary a first resonance frequency of the mobile structure about the first axis.

Abstract: An electrical connection wire connects an electrical connection pad of an electrical chip and an electrical connection pad of a carrier substrate to which the electronic chip is mounted. A dielectric layer surrounds at least the bonding wire. The dielectric layer may be a dielectric sheath or a hardened liquid dielectric material. A dielectric material may also cover at least a portion of the electrical chip and carrier substrate. A liquid electrically conductive material is deposited and hardened to form a local conductive shield surrounding the dielectric layer at the bonding wire.

Abstract: A range detector device may include a pulsed light source configured to emit pulsed light to an object, a detector configured to receive reflected pulsed light from the object, and a processor cooperating with the pulsed light source and the detector. The processor may be configured to generate a measured range value to the object, and generate an estimated statistical value for a spread of possible range values based upon a characteristic of the pulsed light source.

Abstract: A driver includes a high-side driver transistor coupled between supply voltage and the gate drive nodes and provides a first charge current to a high side gate node of the high-side driver transistor until the gate drive node reaches a first gate drive threshold. Then a second charge current is provided to the high side gate node that is less than the first charge current. The gate drive node is limited to a first clamped threshold for a delay time. A gate drive current rise signal sets the value of the second charge current that charges the high side gate node and after the delay time the gate drive voltage is limited to a second clamped threshold greater than the first clamped threshold but less than the supply voltage. A gate drive programmable control signal sets the value of the second clamped threshold.

Abstract: A method of detecting a cold-boot attack includes transferring, into a first volatile memory of an integrated circuit, a pattern stored in a non-volatile memory of the integrated circuit. Power to the non-volatile memory is periodically interrupted and an indication of a number of errors in the non-volatile memory is generated. The indication of the number of errors is compared to one or more thresholds. An occurrence of a cold-boot attack is detected based on the comparison. The pattern may be reloaded into the first volatile memory before each power interruption. The pattern may be selected so that the number of errors varies according to the integrated circuit temperature.

Abstract: An output stage of an output buffer circuit includes a first drive transistor and a first cascode transistor (coupled in series between a first supply node and an output node) and a second drive transistor and a second cascode transistor (coupled in series between the output node and a second supply node). Gates of the first and second cascode transistors are biased with first and second bias voltages, respectively. The first bias voltage equals the first supply voltage at the first supply node when the first supply voltage is less than a threshold, and is fixed at a fixed voltage for any first supply voltage exceeding the threshold voltage. The second bias voltage equals a fixed voltage when the first supply voltage is less than a threshold voltage, and is offset from the first supply voltage by a fixed difference for any first supply voltage exceeding the threshold.

Abstract: A process for manufacturing an interaction system of a microelectromechanical type for a storage medium, the interaction system provided with a supporting element and an interaction element carried by the supporting element, envisages the steps of: providing a wafer of semiconductor material having a substrate with a first type of conductivity and a top surface; forming a first interaction region having a second type of conductivity, opposite to the first type of conductivity, in a surface portion of the substrate in the proximity of the top surface; and carrying out an electrochemical etch of the substrate starting from the top surface, the etching being selective with respect to the second type of conductivity, so as to remove the surface portion of the substrate and separate the first interaction region from the substrate, thus forming the supporting element.

Abstract: A method can be used for managing a power supply voltage on an output power supply pin of a USB Type-C source device coupled to a USB Type-C receiver device via a USB Type-C cable. A first measurement of a first voltage on a channel configuration pin of the cable is performed when the receiver device is not powered and a second measurement of a second voltage on the channel configuration pin is performed when the receiver device is powered. A difference between the first and second voltages is calculated and the power supply voltage is modified as a function of a value of the difference.

Abstract: Disclosed herein is a MEMS device including a fixed structure, a mobile structure, and deformable structures extending therebetween. The deformable structures have first ends anchored along X and Y axes of the fixed structure, and have second ends anchored offset from the X and Y axes of the fixed structure. The deformable structures are shaped so as to curve from their anchoring points along the mobile structure back toward the mobile structure, to extend along the perimeter of the mobile structure, and to then curve away from the mobile structure and toward their anchoring points along the fixed structure. Each deformable structure has two piezoelectric elements that extend along the length of that deformable structure, with one piezoelectric element having a greater length than the other piezoelectric element.

Abstract: A capacitive panel is scanned with an AC signal having pulses at a first frequency to produce a first frame of mutual capacitance data and pulses at a second frequency, different from the first frequency, to produce a second frame of mutual capacitance data. If neither the first nor second frames of mutual capacitance data is perturbed by noise, then data of the first and second frames of mutual capacitance data is averaged. The averaged data is then used in centroid processing.

Abstract: A circuit is for coupling test access port (TAP) signals to a Joint Test Action Group (JTAG) interface in an integrated circuit package. An nTRST pin receives a test reset signal, a TMS pin receives a test mode select signal, a testing test access port (TAP) has a test reset signal input and a test mode select signal input, and a debuging test access port (TAP) has a test reset signal input coupled to the nTRST pin and a test mode select signal input coupled to the TMS pin. An inverter has an input coupled to the nTRST pin and an output coupled to the test reset signal input of the testing TAP, and an AND gate has a first input coupled to the output of the inverter, a second input coupled to the TMS pin, and an output coupled to the test mode select input of the testing TAP.

Abstract: Disclosed herein is a control system for a laser scanning projector. The control system includes a mirror controller generating a mirror synchronization signal for an oscillating mirror apparatus based upon a mirror clock signal. The control system also includes laser modulation circuitry for generating a laser synchronization signal as a function of a laser clock signal, and generating control signals for a laser that emits a laser beam that impinges on the oscillating mirror apparatus. Synchronization circuitry is for generating the laser clock signal and sending the laser clock signal to the laser modulation circuitry, receiving the mirror synchronization signal from the mirror controller, receiving the laser synchronization signal from the laser modulation circuitry, and modifying frequency and phase of the laser clock signal for the laser as a function of the mirror synchronization signal and the laser synchronization signal.

Abstract: A test circuit is operable in ATPG mode and LBIST mode. The test circuit includes a clock selection circuit. The clock selection circuit includes clock logic circuitry to receive an LBIST mode signal and an ATPG mode signal and to generate an indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode, a multiplexing circuit to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock, and a clock gate circuit enabled in response to enable signals. The enable signals are an inverse of a selected one of the ATPG clock and the functional clock. The clock gate circuit receives the indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode and generates a test clock as a function of the indication.

Abstract: An electronic device includes a support wafer, an electronic chip and an encapsulating block for the electronic chip above the support wafer. The support wafer is provided with a first network of electrical connections and a second network of electrical connections formed solely by tracks. First electrical connection elements are interposed between first front electrical contacts of the electronic chip and rear electrical contacts of the first network. Second electrical connection elements are interposed between second front electrical contacts of the electronic chip and internal electrical contact zones of the tracks of the second network. The first network includes front external electrical contacts and the tracks exhibiting external electrical contact zones.

Abstract: An image sensor chip includes a semiconductor layer intended to receive illumination on a back face and comprising a matrix of pixels on a front face. An interconnection structure is arranged on the front face and a carrier is attached to the interconnection structure with a first face of the carrier facing the front face. An annular trench, arranged on a perimeter of the image sensor chip, extends from a second face of the carrier through an entire thickness of the carrier and into the interconnection structure. A via opening, arranged within the annual trench, extends from the second face of the carrier through the entire thickness of the carrier to reach a metal portion of the interconnection structure. The via opening an annual trench are lined with an insulating layer. The via opening include a metal conductor making an electrical connection to the metal portion.

Abstract: A level-shifter circuit operates to shift an input signal referenced to a first set supply voltages to generate an output signal referenced to a second set of supply voltages. The output signal from the level-shifter circuit is latched by a latching circuit. A logic gate has a first input configured to receive the input signal, a second input configured to receive a feedback signal and an output coupled to a input of the level shifting circuit. A feedback circuit has a first input configured to receive the output signal, a second input configured to receive the input signal and an output configured to generate the feedback signal. The feedback circuit operates to sense an uncontrolled switching event of the output signal occurring in the absence of a switching of the input signal and apply, in response thereto, the feedback signal to cancel the uncontrolled switching event.

Abstract: A capacitive element is fabricated by forming a sacrificial trench isolation and directionally etching through the sacrificial trench isolation and into an underlying semiconductor substrate to form an electrode trench. The electrode trench is then clad with an insulating material and filled with a conductive material. The conductive fill provided one capacitor electrode and the semiconductor substrate forms another capacitor electrode, with the insulating material cladding forming the capacitor dielectric layer.

Abstract: Disclosed herein is a method including receiving multi-axis accelerometer data representing a potential step taken by a user of an electronic device. The method also includes determining whether the potential step represented by the multi-axis accelerometer data is a false. This determination is made by calculating statistical data from the multi-axis accelerometer data, and applying a decision tree to the statistical data to perform a cross correlation that determines whether the potential step is a false positive. If the potential step is not a false positive, a step detection process is performed to determine whether the potential step is a countable step and, if the potential step is found to be a countable step, a step counter is incremented.

Abstract: A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.

Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.