Patents Assigned to STMicroelectronics AS
  • Patent number: 10227040
    Abstract: A method for vehicle parking assistance during a parking maneuver of the vehicle includes detecting an obstacle in a detection space outside the vehicle. Successive measurements are taken of the distance or distances separating the vehicle and the obstacle and the position or positions of the obstacle relative to the vehicle. Depending on the results of the measurements, human speech voice messages are generated that provide parking assistance. The voice messages are broadcasted in the passenger compartment of the vehicle.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: March 12, 2019
    Assignee: STMICROELECTRONICS (GRAND OUEST) SAS
    Inventor: Arnaud Pouliquen
  • Patent number: 10228555
    Abstract: The present disclosure provides a system and method for controlling operation of a resonance MEMS mirror. The system and method includes activating either an in-plane or staggered MEMS mirror via sets of activation pulses applied to the MEMS mirror, detecting current at the MEMS mirror, generating a window for detecting a change in a direction of the current at the MEMS mirror, and terminating the window and the activation pulse if a change in the current direction is detected during the window. In some embodiments, two sets of activation pulses are applied to the MEMS mirror.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: March 12, 2019
    Assignee: STMicroelectronics Ltd
    Inventor: Sason Sourani
  • Patent number: 10229484
    Abstract: Tone mapping is applied to pixels of a digital image. A luminance value of a pixel is determined based on whether one or more pixel intensity values of a pixel in a color space are within a pixel saturation range. A pixel gain is determined based on the determined luminance value of the pixel, and the determined pixel gain is applied to the pixel. The luminance value may also or instead be determined based on whether one or more of the pixel intensity values is within a pixel black-out range. A weight may be employed to determine the luminance value.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: March 12, 2019
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Grégory Roffet, Mathieu Thivin
  • Patent number: 10229880
    Abstract: A stack including a dual-passivation is etched locally so as to reveal contact pads of an integrated circuit which are situated above a last metallization level of an interconnection part of the integrated circuit. This stack serves to protect the integrated circuit against a breakdown of at least one dielectric region, at least in part porous, separating two electrically conducting elements of the interconnection part of the integrated circuit. Such a breakdown may occur due to electrical conduction assisted by the presence of defects within the at least one dielectric region.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: March 12, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Jean-Philippe Escales
  • Patent number: 10231118
    Abstract: A method is provided for performing a management of a multi-subscription SIM module. The multi-subscription SIM module includes at least one memory adapted to store at least a first and a second profile associated with a respective first and a second mobile network operator. The memory includes a volatile portion. The operation of storing includes installing or updating profiles by downloading one or more downloaded profiles from a remote host. The management includes selecting one or more enabled profiles including an application to be executed and allocating a partition of the volatile portion of the memory to the one or more enabled profile.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: March 12, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Amedeo Veneroso
  • Patent number: 10227233
    Abstract: A microelectromechanical device having a first substrate of semiconductor material and a second substrate of semiconductor material having a bonding recess delimited by projecting portions, monolithic therewith. The bonding recess forms a closed cavity with the first substrate. A bonding structure is arranged within the closed cavity and is bonded to the first and second substrates. A microelectromechanical structure is formed in a substrate chosen between the first and second substrates. The device is manufactured by forming the bonding recess in a first wafer; depositing a bonding mass in the bonding recess, the bonding mass having a greater depth than the bonding recess; and bonding the two wafers.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: March 12, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Giorgio Allegato, Laura Oggioni, Matteo Garavaglia, Roberto Somaschini
  • Patent number: 10230358
    Abstract: In accordance with an embodiment, a method includes receiving an enable signal. After the enable signal is asserted, it is determined whether a soft-start capacitor is electrically connected to an input of a ramp generator circuit while keeping an output of the ramp generator circuit low. If the soft-start capacitor is electrically connected to the input of the ramp generator circuit, a first current is injected into the input of the ramp generator circuit to generate a first voltage ramp at the output of the ramp generator circuit. If the soft-start capacitor is not electrically connected to the input of the ramp generator circuit, a second current is injected to the input of the ramp generator circuit to generate a second voltage ramp at the output of the ramp generator circuit. The second current is smaller than the first current.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: March 12, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventor: Marco Martini
  • Patent number: 10230322
    Abstract: A system in package encloses a sensor and motor driver circuit. In an implementation, the sensor is an integrated circuit micro-electro-mechanical-systems (MEMS) sensor and the driver circuit is a motor driver circuit. Non-motor winding data information is sensed by the MEMS sensor and processed for the purpose of characterizing known fault patterns for motors; characterizing normal operation of the motor; and evaluating continued operation of the motor to detect abnormal motor behavior and instances of motor fault. The motor is driven using PWM control and the information output by the MEMS sensor is sampled at sampling times having a fixed timing relationship relative to the PWM control signals.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: March 12, 2019
    Assignee: STMicroelectronics, Inc.
    Inventors: Cheng Peng, Robert Krysiak
  • Patent number: 10230214
    Abstract: An embodiment circuit includes a diode having a first terminal coupled to a first reference voltage; a first controllable switch coupled between a second terminal of the diode and a second reference voltage; and a capacitive element having a first terminal coupled to the first reference voltage and a second terminal controllably coupled to the second terminal of the diode.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: March 12, 2019
    Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventors: Denise Lee, John Kevin Moore
  • Patent number: 10229508
    Abstract: Method of estimating a position variation of a motion of an apparatus between a first instant and a second instant, said motion including a rotation of the apparatus and said position variation, said position variation including a position and a velocity, wherein estimating said position variation comprises performing a particles filtering for estimating said position and velocity from the probabilistic-weighted average of the particles, said particles filter using a known estimation of said rotation and being parameterized for taking into account a quality of said rotation estimation.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: March 12, 2019
    Assignee: STMICROELECTRONICS SA
    Inventors: Manu Alibay, Stéphane Auberger
  • Patent number: 10231365
    Abstract: A thermal control process for an electronic power device including a multi junction integrated circuit may include defining a first and at least one second groups of junctions, with each group including one first and at least one second junctions, and associating a thermal detector with each group. A first group control may be executed which detects group electric signals representative of the temperature detected by the thermal detectors, processes the group electric signals with reference to a group critical thermal event, identifies a critical group when the corresponding group electric signal detects the critical group thermal event, and generates group deactivating signals suitable for selectively deactivating the first and the at least one second junctions of the identified critical group with respect to the remaining junctions of the integrated circuit.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: March 12, 2019
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS APPLICATION GMBH
    Inventors: Domenico Massimo Porto, Giovanni Luca Torrisi, Manuel Gaertner, Sergio Lecce
  • Patent number: 10230363
    Abstract: A method is used to control an electronic device that includes a switching unit having a main MOS transistor having a substrate, a first conducting electrode and a second conducting electrode coupled to an output terminal. The method includes controlling the main transistor in such a way as to put it into an on state or an off state such that, when the main transistor is in the on state, the substrate and the first conducting electrode of the main transistor are connected to an input terminal and, when the main transistor is in the off state, the first conducting electrode of the main transistor is isolated from the input terminal and a first bias voltage is applied to the first conducting electrode and a second bias voltage is applied to the substrate of the main transistor.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: March 12, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Bruno Gailhard, Michel Cuenca
  • Publication number: 20190072994
    Abstract: A circuit for generating a bandgap voltage includes a circuit module for generation of a base-emitter voltage difference comprising a pair of PNP bipolar substrate transistors which identify a first current path and a second current path. A first current mirror of an n type is connected between the first and second branches and is further connected via a resistance for adjustment of the bandgap voltage to the second bipolar transistor. A second current mirror of a p type is connected between the first and second branches, and connected so that the current mirrors repeat current of each other. In operation to generate the bandgap voltage, current flows from the supply voltage to ground only through said the first and second bipolar substrate transistors.
    Type: Application
    Filed: November 7, 2018
    Publication date: March 7, 2019
    Applicant: STMicroelectronics S.r.l.
    Inventors: Calogero Marco Ippolito, Mario Chiricosta
  • Publication number: 20190074835
    Abstract: A process and temperature variation operating condition that is globally applicable to an integrated circuit die is sensed in a core circuit region to generate a global process and temperature compensation signal. A voltage variation operating condition that is locally applicable to an input/output circuit within a peripheral circuit region of the integrated circuit die is sensed to generate a local voltage compensation signal. More specifically, the localized voltage operating condition is generated as a function of a measured difference in frequency between a first clock signal generated in the peripheral circuit region in response to a supply voltage subject to voltage variation and a second clock signal generated in the core circuit region in response to a fixed bandgap reference voltage. The operation of the input/output circuit is then altered in response to the global process and temperature compensation signal and in response to the local voltage compensation signal.
    Type: Application
    Filed: September 7, 2017
    Publication date: March 7, 2019
    Applicant: STMicroelectronics International N.V.
    Inventors: Prashant Singh, Pratap Narayan Singh
  • Publication number: 20190074830
    Abstract: First and second comparators receive input signals of opposed polarities and drive operation of a switch in response thereto. A first current generator supplies a first current to the switch which, in response to the control of the first and second comparators, applies the first current, alternatively, to a first node or a second node. A second current generator sinks a second current from the first node and a third current generator sinks a third current from the second node. A logic circuit has inputs coupled to the first node and the second node, respectively, receives respective switching signals having fast switching wavefronts and delayed switching wavefronts. The output of logic circuit is configured for switching between a first state and a second state with switching between the first state and the second state triggered by the fast switching wavefronts of the respective switching signals.
    Type: Application
    Filed: September 5, 2018
    Publication date: March 7, 2019
    Applicant: STMicroelectronics S.r.l.
    Inventors: Ignazio Bruno MIRABELLA, Agatino Antonino ALESSANDRO
  • Patent number: 10222819
    Abstract: A reference voltage generator circuit includes a circuit that generates a complementary to absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) current. An output current circuit generates, from the PTAT current, a sink PTAT current sunk from a first node and a source PTAT current sourced to a second node, wherein the sink and source PTAT currents are equal. A resistor is directly connected between the first node and the second node. A divider circuit divides the CTAT voltage to generate a divided CTAT voltage applied to the first node. A voltage at the second node is a fractional bandgap reference voltage equal to a sum of the divided CTAT voltage and a voltage drop across the resistor that is proportional to a resistor current equal to the sink and source PTAT currents.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: March 5, 2019
    Assignee: STMicroelectronics International N.V.
    Inventor: Abhirup Lahiri
  • Patent number: 10225473
    Abstract: A method determines a movement of an apparatus between capturing first and second images. The method includes testing model hypotheses of the movement by for example a RANSAC algorithm, operating on a set of first points in the first image and assumed corresponding second points in the second image to deliver the best model hypothesis. The testing includes, for each first point, calculating a corresponding estimated point using the tested model hypothesis, determining the back-projection error between the estimated point and the second point in the second image, and comparing each back projection error with a threshold. The testing comprises for each first point, determining a correction term based on an estimation of the depth of the first point in the first image and an estimation of the movement between the first and second images, and determining the threshold associated with the first point by using said correction term.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: March 5, 2019
    Assignee: STMICROELECTRONICS SA
    Inventors: Manu Alibay, Stéphane Auberger
  • Patent number: 10222415
    Abstract: Disclosed herein is a test circuit for testing a device under test (DUT). The test circuit receives a test pattern output by the DUT. A content addressable memory (CAM) stores expected test data at a plurality of address locations, receives the test pattern, and outputs an address of the CAM containing expected test data matching the received test pattern. A memory also stores the expected test data at address locations corresponding to the address locations of the CAM. A control circuit causes the memory to output the expected test data stored therein at the address output by the CAM. Comparison circuitry receives the test pattern from the input, and compares that received test pattern to the expected test data output by the control circuit, and generates an error count as a function of a number of bit mismatches between the received test pattern and the expected test data.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: March 5, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Tejinder Kumar, Suchi Prabhu Tandel, Rakesh Malik
  • Patent number: 10224097
    Abstract: Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: March 5, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Ashish Kumar, Vinay Kumar, Kedar Janardan Dhori
  • Patent number: 10225635
    Abstract: A microelectromechanical microphone includes: a substrate; a sensor chip, integrating a microelectromechanical electroacoustic transducer; and a control chip operatively coupled to the sensor chip. In one embodiment, the sensor chip and the control chip are bonded to the substrate, and the sensor chip overlies, or at least partially overlies, the control chip. In another embodiment, the sensor is bonded to the substrate and a barrier is located around at least a portion of the sensor chip.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: March 5, 2019
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Malta) Ltd
    Inventors: Roberto Brioschi, Alex Gritti, Kevin Formosa, Paul Anthony Barbara