Abstract: A digital image processing circuit processes macro-pixels of a digital image. A gain control parameter of each pixel of the macro-pixel of the digital image is determined based on a location of the pixel in the digital image. Relative pixel positions of the pixels of the macro-pixel are determined, the relative pixel positions representing pixel positions with respect to color grids. A gain value of each pixel of the macro-pixel is determined based on the relative pixel positions. The gain values are modified based on the gain control parameters. The modified gains are applied to the pixels of the macro-pixel.

Abstract: Miniature resistive gas detectors incorporate thin films that can selectively identify specific gases when heated to certain characteristic temperatures. A solid state gas sensor module is disclosed that includes a gas sensor, a heater, and a temperature sensor, stacked over an insulating recess. The insulating recess is partially filled with a support material that provides structural integrity. The solid state gas sensor module can be integrated on top of an ASIC on a common substrate. With sufficient thermal insulation, such a gas detector can be provided as a low-power component of mobile electronic devices such as smart phones. A method of operating a multi-sensor array allows detection of relative concentrations of different gas species by either using dedicated sensors, or by thermally tuning the sensors to monitor different gas species.

Abstract: An image sensor has an array of light-sensitive pixels. Each pixel of the array includes a photodiode and a plurality of capacitors configured to store charge from the photodiode. The image sensor has an address decoder, coupled to the array of light-sensitive pixels. In at least one mode of operation, portions of the array of light-sensitive pixels to capture respective image exposures. The portions may include interlaced rows of pixels of the array of light-sensitive pixels, blocks of rows of pixels of the array of light-sensitive pixels, interlaced columns of pixels of the array of light-sensitive pixels, interlaced columns and rows of pixels of the array of light-sensitive pixels, blocks of columns and rows of pixels of the array of light-sensitive pixels, etc.

Abstract: An electronic circuit is for switching a power transistor having a drain coupled to a drain node, a source coupled to a lower voltage supply, and a gate coupled to a gate node. The electronic circuit includes first current generation circuitry to generate a first current to flow into the gate node in response to assertion off an ON signal, the first current being substantially constant. Second current generation circuitry generates a second current to flow into the gate node in response to deassertion of an OFF signal, the second current being inversely proportional to a gate to source voltage of the power transistor. First comparison circuitry compares a drain voltage at the drain node to a reference voltage, and activates third current generation circuitry to generate a third current to flow into the gate node when the drain voltage is less than the reference voltage.

Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.

Abstract: A method for controlling a low-power state of a pair of serial interfaces using a pair of flow-control signal lines may include enabling a first of the flow-control lines by a first one of the interfaces for signaling a transmission request to the second interface. The method may also include, in response to the transmission request, waking up to a live state from a low-power state and enabling a second flow-control line for signaling a transmission authorization to the first interface. In response to the transmission authorization, the method may include initiating a transmission of a message to the second interface, and upon reaching an offset before the end of the message transmission, disabling the first flow-control line by the first interface. The method may also include, at the end of the message transmission, disabling the second flow-control line and going back into the low-power state.

Abstract: A non-porous dielectric barrier is provided between a porous portion of a dielectric region and an electrically conductive element of an interconnect portion of an integrated circuit. This non-porous dielectric barrier protects the integrated circuit from breakdown of the least one dielectric region caused by electrical conduction assisted by the presence of defects located in the at least one dielectric region.

Abstract: A switching converter converts an input signal to a regulated output signal using a switch and a transformer with a primary winding and a secondary winding. A wake up management circuit receives a transformer demagnetization signal and forces by wake up pulses the switch on when the switching converter operates in a burst mode. Sampled values of the transformer demagnetization signal are received. A setting circuit sets a first peak value of the current of the primary winding. A comparison circuit compare the sampled values with a voltage threshold and the preceding sampled value. In response thereto, the first peak value of the primary winding current is either maintained or a new peak value is set.

Abstract: A photodiode has an active portion formed in a silicon substrate and covered with a stack of insulating layers successively including at least one first silicon oxide layer, an antireflection layer, and a second silicon oxide layer. The quantum efficiency of the photodiode is optimized by: determining, for the infrared wavelength, first thicknesses of the second layer corresponding to maximum absorptions of the photodiode, and selecting, from among the first thicknesses, a desired thickness, eoxD, so that a maximum manufacturing dispersion is smaller than a half of a pseudo-period separating two successive maximum absorption values.

Abstract: An infrared high-pass plasmonic filter includes a copper layer interposed between two layers of a dielectric material. An array of patterned openings extend through the copper layer and are filled with the dielectric material. Each patterned opening is in the shape of a greek cross, with the arms of adjacent patterns being collinear. A ratio of the width to the length of each arm is in the range from 0.3 to 0.6, and the distance separating the opposite ends of arms of adjacent patterns is shorter than 10 nm.

Abstract: A device disclosed herein includes a feedback measuring circuit to measure a signal flowing through a movable MEMS mirror. Processing circuitry determines a time at which the signal indicates that a capacitance of the movable MEMS mirror is substantially at a maximum capacitance. The processing circuitry also determines, over a window of time extending from the time at which the signal indicates that the capacitance of the movable MEMS mirror is substantially at the maximum to a given time, a total change in capacitance of the movable MEMS mirror compared to the maximum capacitance. The processor further determines the capacitance at the given time as a function of the total change in capacitance, and determines an opening angle of the movable MEMS mirror as a function of the capacitance at the given time.

Abstract: A power converter includes an input and an output with an energy storage circuit and a power switching circuit coupled between the input and the output. A feedback circuit generates a feedback voltage which is differentially compared to a reference in an error amplifier circuit to generate an error amplification signal. A comparator circuit generates a control signal for controlling on/off of the power switching circuit based on a first comparison signal related to the error amplification signal and a second comparison signal related to a charging current of the energy storage circuit. A regulating circuit is coupled between an output of the error amplifier circuit and an input of the comparator circuit for receiving the first comparison signal, the regulating circuit is configured to couple a voltage compensation signal related to an input voltage received by the input to an output of the error amplifier, so as to reduce a variation amount of the error amplification signal when the input voltage varies.

Abstract: Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator.

Abstract: A module incorporated within a system-on-a-chip operating in a steady-state power supply phase is powered by supplying to the module a regulated power supply voltage obtained from a feedback control loop. The receives a main power supply voltage and a negative feedback voltage. The negative feedback voltage is generated inside the system-on-a-chip starting from an effective supply voltage of the module and from a setpoint signal corresponding to a desired regulated power supply voltage.

Abstract: An active high gain filter includes high value resistances in feedback implemented using a negative resistance circuit configuration. The high value resistance is implemented using two or smaller resistances connected in the negative resistance circuit configuration. This implementation permits integration of the filter circuit using less occupied area while still providing an accurate transfer function response.

Abstract: A video and/or audio decoder provided with a first terminal for supplying an analog audio and/or video signal, including: a first circuit capable of supplying a digital signal which is an image of said analog signal; a digital-to-analog converter capable of receiving as an input said digital signal; an amplifier coupling a second output terminal of the digital-to-analog converter to the first terminal; and a second circuit capable of comparing a signal representative of the voltage or current level on the first terminal with a reference signal, and of deducing therefrom whether the first terminal is connected or not to an analog input terminal of a video signal display and/or audio signal playing device.

Abstract: A color calibration device for a laser scanning apparatus includes a compensation unit configured to electronically compensate for positional errors of the three-color laser source. The compensation unit includes an emitted light detector configured to measure a power of an emitted light beam. A calibration unit coupled to the emitted light detector has a controller configured to generate a quantity correction value for the three-color laser source. A laser source control element is configured to generate a control quantity for the three-color laser source, based on the quantity correction value. A dominant color detector is configured to detect any dominant color in the light beam being projected and actuate the controller for the dominant color.

Abstract: Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted voltage results from a capacitive coupling to the word line in that row. The capacitive coupling is implemented by running the metal line of the power supply line for the cell supply voltage and the metal line for the word line adjacent to each other in a common metallization level. The selective voltage boost is controlled in response to operation of a modified memory cell exhibiting a deteriorated write margin. An output of the modified memory cell is compared to a threshold to generate a signal for controlling the selective voltage boost. Word line under-voltage circuitry is further provided to control application of an under-voltage to the word line.

Abstract: An integrated circuit is formed using a substrate of a silicon-on-insulator type that includes a carrier substrate and a stack of a buried insulating layer and a semiconductor film on the carrier substrate. A first region without the stack separates a second region that includes the stack from a third region that also includes the stack. An MOS transistor has a gate dielectric region formed by a portion of the buried insulating layer in the second region and a gate region formed by a portion of the semiconductor film in the second region. The carrier substrate incorporates doped regions under the first region which form at least a part of a source region and drain region of the MOS transistor.

Abstract: A pixel arrangement includes a photodiode, a reset transistor configured to be controlled by a reset signal and coupled to a reset input voltage, a transfer gate transistor configured to transfer charge from the photodiode to a node, wherein the transfer gate transistor is controlled by a transfer gate voltage, and a source follower transistor controlled by the voltage on the node and coupled to a source follower voltage. A capacitor is coupled between the node and an input voltage. During a read operation the input voltage is increased to boost the voltage at the node. The increased input voltage may, for example, be one the reset input voltage, said source follower voltage, said transfer gate voltage and a boosting voltage.