Abstract: A semiconductor device may include a semiconductor wafer, and a reference circuit carried by the semiconductor wafer. The reference circuit may include optical DUTs, a first set of photodetectors coupled to outputs of the optical DUTs, an optical splitter coupled to inputs of the optical DUTs, and a second set of photodetectors coupled to the optical splitter. The optical splitter is to be coupled to an optical source and configured to transmit a reference optical signal to the first set of photodetectors via the optical DUTs and the second set of photodetectors.

Abstract: An integrated circuit integrated on a semiconductor material die and adapted to be at least partly tested wirelessly, wherein circuitry for setting a selected radio communication frequencies to be used for the wireless test of the integrated circuit are integrated on the semiconductor material die.

Abstract: An NFC device may include a first and second controller interfaces, a first communication channel coupled to the first controller interface, and a second communication channel connected to the second controller interface. A secure element may include a secure element interface connected to the first communication channel and encryption/decryption circuitry configured to encrypt data to be sent on the first communication channel for being framed into the encrypted frames and to decrypt encrypted data extracted from the encrypted frames and received from the first communication channel. The secure element may also include management circuitry configured to control the encryption/decryption circuitry for managing the encrypted communication with the NFC controller.

Abstract: In one implementation, a capacitive sensing structure comprises rows of first sensors electrically coupled together and columns of second sensors electrically coupled together, wherein the first sensors include: a first arm extending in a first direction and having a first plurality of finger structures extending therefrom, a second arm extending in the first direction and having a second plurality of finger structures extending therefrom, and an end portion connecting the arms, wherein the first sensors define open regions that are occupied by the second sensors. In a second implementation, a capacitive sensing structure comprises rows of first sensors and columns of second sensors, wherein each of the first sensors includes an elongated portion having finger structures extending therefrom, and wherein each of the second sensors includes a primary portion connected to secondary portions via arms, wherein the secondary portions occupy gaps defined by the finger structures of the first sensors.

Abstract: A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.

Abstract: A sensing device is for sensing an outer surface of a roll of material. An infrared (IR) laser source is configured to direct IR laser radiation to the outer surface of the roll of material. A single photon avalanche diode (SPAD) detector is configured to receive reflected IR laser radiation from the outer surface of the roll of material. A controller is coupled to the IR laser source and the SPAD detector to determine a distance to the outer surface of the roll of material based upon a time-of-flight of the IR laser radiation.

Abstract: A locked loop circuit includes a controlled oscillator generate an output signal having a frequency set by an analog control signal. The analog control signal is generated by a first digital-to-analog converter (DAC) in response to a digital control signal and a bias compensation current signal. The bias compensation current signal is generated by a second DAC in response to a compensation control signal and a bias reference current. A compensation circuit adjusts the compensation control signal during compensation mode in response to a comparison of a frequency of the output signal to a frequency of a reference signal so as to drive the frequency of the output signal toward matching a desired frequency. The bias compensation current signal associated with the frequency match condition during compensation mode is then used during locked loop mode.

Abstract: One or more embodiments are directed to system in package (SiP) for optical devices, including proximity sensor packaging. One embodiment is directed to an optical sensor that includes a substrate and a sensor die. A through-hole extends through the substrate, and a trench is formed in a first surface of the substrate and is in fluid communication with the through-hole. The sensor die is attached to the first surface of the substrate and covers the first through-hole and a first portion of the trench. A second portion of the trench is left uncovered by the sensor die.

Abstract: An electrostatic discharge protection device includes first and second diodes series-connected between first and second connection terminals. A third connection terminal is coupled to a junction of the first and second diodes. A capacitor is connected in parallel with the first and second diodes between the first and second terminals.

Abstract: A method of detecting sequences of multi-level encoded symbols. The multi-level encoded symbols are mapped and modulated with a modulation scheme having a number of constellation points identified by a sequence of bits arranged in at least a first and a second group. The first group is encoded with a first encoding scheme, and the second group is encoded with a second coding scheme, and the multi-level encoded symbols are transmitted by multiple transmitting sources and received as a received vector by multiple receiving elements. A first set of candidate sequences is selected and a first set of probability information is calculated for the first set of candidate sequences. Then the first group of bits of the symbols are decoded. The decoded bits of the first group are re-encoded and used to select a sub-set of constellation points.

Abstract: A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.

Abstract: The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.

Abstract: A package for a device to be inserted into a solid structure may include a building material that includes particles of one of micrometric and sub-micrometric dimensions. The device may include an integrated detection module having at least one integrated sensor and the package arranged to coat at least one portion of the device including the integrated detection module. A method aspect includes a method of manufacturing the device. A system aspect is for monitoring parameters in a solid structure that includes the device.

Abstract: An electronic device disclosed herein includes a current comparator to generate an output current based upon a difference between a current flowing in an output branch and a current flowing in an input branch. A pair of transistors is coupled to an output of the current comparator. A first amplifier has inputs coupled to the pair of transistors and to a reference voltage, the first amplifier being configured to subtract the reference voltage from a voltage across the pair of transistors and output a difference voltage. A second amplifier has inputs coupled to the difference voltage and to the reference voltage, the second amplifier being configured to subtract the difference voltage from the reference voltage and output a pulse skipping mode reference signal.

Abstract: An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.

Abstract: A read-amplifier circuit includes a core with a first input and a second input that are intended to receive in a measurement phase a differential signal arising from a first bit line and from a second bit line of the memory device. The circuit also includes a memory element with two inverters coupled in a crossed manner. The first and second inputs are respectively connected to two of the power supply nodes of the inverters via two transfer capacitors. A first controllable circuit is configured to temporarily render the memory element floating during an initial phase preceding the measurement phase and during the measurement phase.

Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filled with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

Abstract: Improved fin field effect transistor (FinFET) devices and methods for fabrication thereof. In one aspect, a method for fabricating a FinFET device comprises: a silicon substrate on which a silicon epitaxial layer is grown is provided. Sacrificial structures on the substrate are formed from the epitaxial layer. A blanket silicon layer is formed over the sacrificial structures and exposed substrate portions, the blanket silicon layer having upper and lower portions of uniform thickness and intermediate portions interposed between the upper and lower portions of non-uniform thickness and having an angle of formation. An array of semiconducting fins is formed from the blanket silicon layer and a non-conformal layer formed over the blanket layer. The sacrificial structures are removed and the resulting void filled with isolation structures under the channel regions. Source and drain are formed in the source/drain regions during a fin merge of the FinFET.

Abstract: A voltage source wherein at least one first switch couples a first node of the voltage source to a node of application of at least one potential of a power supply voltage, and at least one first capacitive element couples the first node or a second node of the voltage source to a control node of the first switch.

Abstract: A method for calibrating a resistance value comprises the steps of measuring a value of a reference capacitor, and adjusting a variable resistor based on the measured value of the reference capacitor. The method may more specifically comprise the steps of directing a constant current through the reference capacitor during a reference time interval; after the reference time interval, directing the constant current through the variable resistor; and varying the variable resistor value progressively by varying a control signal until a voltage of the variable resistor reaches a voltage of the reference capacitor.