Abstract: An embodiment of a data-read path includes a defect detector and a data-recovery circuit. The defect detector is operable to identify a defective region of a data-storage medium, and the data-recovery circuit is operable to recover data from the data-storage medium in response to the defect detector. For example, such an embodiment may allow identifying a defective region of a data-storage disk caused, e.g., by a scratch or contamination, and may allow recovering data that was written to the defective region.

Abstract: The present disclosure is directed to a microfluidic die that includes a plurality of heaters above a substrate, a plurality of chambers and nozzles above the heaters, a plurality of first contacts coupled to the heaters, and a plurality of second contacts coupled to the heaters. The plurality of second contacts are coupled to each other and coupled to ground. The die includes a plurality of contact pads, a first signal line coupled to the plurality of second contacts and to a first one of the plurality of contact pads, and a plurality of second signal lines, each second signal line being coupled to one of the plurality of first contacts, groups of the second signal lines being coupled together to drive a group of the plurality of heaters with a single signal, each group of the second signal lines being coupled to a remaining one of the plurality of contact pads.

Abstract: A capacitive discharge circuit includes a line having a capacitance, a switched capacitor circuit including a capacitor, a switched circuit coupled to the line, and a voltage regulator coupled between the switched capacitor circuit and the switched circuit. A controller operates the switched capacitor circuit and switched circuit to in a first phase, charge the capacitor by coupling the capacitor between a common mode and a power supply, and in a second phase, discharge the capacitor by coupling the voltage regulator in series with the capacitor between the power supply node a ground. The controller is also configured to in a third phase, charge the capacitor by coupling the capacitor between the common mode and the power supply, and in a fourth phase, share charge between the line and the capacitor by coupling the voltage regulator and the capacitor in series between the line and the ground.

Abstract: An integrated circuit includes at least two identical, synchronous and independent oscillator circuits that are coupled one to one in parallel with each other at homologous oscillating nodes of the respective oscillator circuits. The coupling in parallel is made using at least one coupling track that is configured so as to not introduce any phase shift or to introduce a very small phase shift.

Abstract: Disclosed herein is an electronic device including a substrate having a conductive area formed thereon. A first molding level is stacked on the substrate. A die is formed on the substrate and within the first molding level. A second molding level is stacked on the first molding level. At least one passive component is within the second molding level. A conductive structure extends between the second molding level and the substrate and electrically couples the at least one passive component to the conductive area.

Abstract: A circuit includes a counter circuit, a logic circuit, and a clock divider. The counter circuit includes a clock divider counter to be loaded with most significant bits of a divider value, and decremented at a same edge of each pulse of a clock signal. The logic circuit compares a value contained in the divider counter to a reference value and generates an end count signal as a function of the value contained in the divider counter matching the reference value, and transitions a toggle signal at a same edge of each pulse of the end count signal. The clock divider counter is reloaded with the most significant bits of the divider value as a function of the end count signal. The clock divider generates a divided version of the clock signal as a function of the toggle signal.

Abstract: An electronic device includes a carrier substrate, a first electronic chip and a second chip. The first chip is mounted on the carrier substrate via interposed electrical connection elements electrically connecting a front electrical connection network of the first chip and an electrical connection network of the carrier substrate. The second chip is mounted on the first chip via interposed electrical connection elements electrically connecting a front electrical connection network of the second chip and a back electrical connection network of the first chip Electrical connection wires electrically connect the back electrical connection network of the first chip to the electrical connection network of the carrier substrate.

Abstract: A load-sensing device is arranged in a package forming a chamber. The package has a deformable substrate configured, in use, to be deformed by an external force. A sensor unit is positioned in direct contact with the deformable substrate and is configured to detect deformations of the deformable substrate. An elastic element within of the chamber is arranged to act between the package and the sensor unit to generate, on the sensor unit, a force keeping the sensor unit in contact with the deformable substrate. The deformable substrate may be a base of the package, and the elastic element may be a metal lamina arranged between the lid of the package and the sensor unit. The sensor unit may be a semiconductor die integrating piezoresistors.

Abstract: A device protects an incoming multimedia signal with a protection that is controllable and configured for enabling or disabling an application for an interface protection on an outgoing signal coming from the incoming signal. An output interface is configured for delivering the outgoing signal on an output. An authorization process is performed for authorizing or otherwise a control over the enabling or disabling of the interface protection application depending on security rules.

Abstract: The invention relates to an integrated circuit (1), comprising: a field-effect transistor (2), comprising: first and second conduction electrodes (201, 202); a channel zone (203) arranged between the first and second conduction electrodes; a gate stack (220) arranged vertically in line with the channel zone, and comprising a gate electrode (222); an RRAM-type memory point (31) formed under the channel zone, or formed in the gate stack under the gate electrode.

Abstract: A device for transmitting a signal over a serial link includes a transmission processor to carry out, before transmission over the serial link, a scrambling process on successive initial packets of the signal to form a scrambled packet for each initial packet. The transmission processor includes an encoding circuit to carry out an encoding process on each initial packet to deliver an encoded packet. The encoding process includes, for each current initial packet starting from the second, encoding of the current initial packet with the preceding scrambled packet. Calculation circuitry determines, for each initial packet, a bit disparity of the encoded packet and determination of a cumulative bit disparity. Comparison circuitry carries out a comparison process involving the bit disparity of the encoded packet and the cumulative disparity, with the scrambled packet being the encoded packet or the inverted encoded packet, depending on the result of the comparison process.

Abstract: A circuit for biasing non-volatile memory cells includes a dummy decoding path between a global bias line and a biasing node, a reference current generator coupled to the dummy decoding path and configured to supply a reference current, a biasing stage configured to set a cell bias voltage on the biasing node, and a compensation stage configured to compensate a current absorption of the biasing stage at the biasing node so that the reference current will flow through the dummy decoding path.

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Abstract: A microelectromechanical device includes: a body; a movable mass, elastically coupled to the body and oscillatable with respect to the body according to a degree of freedom; a frequency detector, configured to detect a current oscillation frequency of the movable mass; and a forcing stage, capacitively coupled to the movable mass and configured to provide energy to the movable mass through forcing signals having a forcing frequency equal to the current oscillation frequency detected by the frequency detector, at least in a first transient operating condition.

Abstract: According to an embodiment, a circuit includes a protection voltage generator coupled to a first voltage node, a second voltage node, and a ground voltage node, the protection voltage generator configured to generate a plurality of protection voltages at a first plurality of nodes based on the first voltage node and the second voltage node, and a voltage protection ladder coupled between the first voltage node and a low voltage circuit, the voltage protection ladder coupled to the plurality of protection voltages at the first plurality of nodes, the voltage protection ladder configured to generate a first low voltage based on the first voltage node and the plurality of protection voltages.

Abstract: An image processing system includes a first processor that acquires frames of image data. For each frame of data, the first processor generates a Gaussian pyramid for the frame of data, extract histogram of oriented gradient (HOG) descriptors for each level of the Gaussian pyramid, compresses the HOG descriptors, and sends the compressed HOG descriptors. A second processor is coupled to the first processor and is configured to receive the compressed HOG descriptors, aggregate the compressed HOG descriptors into windows, compare data of each window to at least one stored model, and generate output based upon the comparison.

Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.

Abstract: Embodiments of the present disclosure are directed to optical packages having a package body that includes a light protection coating on at least one surface of a transparent material. The light protection coating includes one or more openings to allow light to be transmitted to the optical device within the package body. In one embodiment, the light protection coating and the openings allow substantially perpendicular radiation to be directed to the optical device within the package body. In one exemplary embodiment the light protection coating is located on an outer surface of the transparent material. In another embodiment, the light protection coating is located on an inner surface of the transparent material inside of the package body.

Abstract: A three-dimensional photonic integrated structure includes a first semiconductor substrate and a second semiconductor substrate. The first substrate incorporates a first waveguide and the second semiconductor substrate incorporates a second waveguide. An intermediate region located between the two substrates is formed by a one dielectric layer. The second substrate further includes an optical coupler configured for receiving a light signal. The first substrate and dielectric layer form a reflective element located below and opposite the grating coupler in order to reflect at least one part of the light signal.

Abstract: A Schmitt trigger circuit having an input coupled to a current summing junction. A trickle current source generates a trickle current applied to the current summing junction. A bandgap current source generates a bandgap current applied to the current summing junction (wherein the bandgap current is fixed when a supply voltage exceeds a threshold). A variable current source generates a variable current applied to the current summing junction (wherein the variable current varies dependent on the supply voltage). At the current summing junction, the variable current is offset against the trickle and bandgap currents with respect to generating a voltage that is sensed at the Schmitt trigger circuit input.