Abstract: An electronic device includes a support plate having a mounting face and an electrical connection network. An integrated circuit chip is mounted on the mounting face and linked to the electrical connection network. An en encapsulation block embeds the integrated circuit chip. An additional element made of an electrically conductive material is at least partly embedded within the encapsulation block. The additional conductive element has a main portion extending parallel to the support plate and has a secondary portion that is linked electrically to the integrated circuit chip. An opening is formed in the encapsulation block, and the secondary portion extends into that opening to make the electrical link. The additional conductive element may be an antenna.

Abstract: A distributed active transformer includes an input transformer set and an output transformer set. Active stages are coupled between a transformer in the input transformer set and a transformer in the output transformer set. The input and output transformer sets are each configured as a slab transformer. The input slab transformer includes a single primary slab and many secondary slabs. The output slab transformer includes many primary slabs and a single secondary slab.

Abstract: A structure of insulation between photodiodes formed in a doped semiconductor layer of a first conductivity type extending on a doped semiconductor substrate of the second conductivity type, the insulating structure including a trench crossing the semiconductor layer, the trench walls being coated with an insulating layer, the trench being filled with a conductive material and being surrounded with a P-doped area, more heavily doped than the semiconductor layer.

Abstract: An electronic package includes a substrate having opposing first and second surfaces. Conductive areas are on a first surface of the substrate and include at least one edge conductive area. A plurality of conductive bumps are on the second surface of the substrate and coupled to respective ones of the conductive areas. An integrated circuit (IC) is carried by the substrate. Bond wires are coupled between the IC and respective ones of the conductive areas. An encapsulating material is over the IC and adjacent portions of the substrate. A conductive layer is on the encapsulating material, and at least one conductive body is coupled between the at least one edge conductive area and the conductive layer.

Abstract: Methods and systems are disclosed for the operation of wireless communication networks, in which communication channels can have possibly overlapping bandwidths of different sizes, including sensor networks operating by the IEEE 802.11ah standard. A first method of signaling to negotiate the channel bandwidth conveys the needed information in the SIG field of the PPDUs of duplicate RTS/CTS frames, and uses the SIG field of PPDUs of duplicated data, control and management frames to perform transmit opportunity protection. A second method of signaling to negotiate the channel bandwidth conveys the needed information in the scrambling sequence field of PPDUs of duplicate RTS, and uses the scrambling sequence field of PPDUs of duplicated data, control and management frames to perform transmit opportunity protection.

Abstract: A method includes: writing first data in a first partition of a first memory module and second data in a first partition of a second memory module, and selectively operating the first and second memory modules in a first operating mode and a second operating mode. The first operating mode includes writing parity bits for the first data in a second partition of the second memory module and parity bits for the second data in a second partition of the first memory module. The second operating mode includes writing further data instead of parity bits in the second partition of one or both the first memory module and the second memory module.

Abstract: A method for manufacturing a protective layer for protecting an intermediate structural layer against etching with hydrofluoric acid, the intermediate structural layer being made of a material that can be etched or damaged by hydrofluoric acid, the method comprising the steps of: forming a first layer of aluminum oxide, by atomic layer deposition, on the intermediate structural layer; performing a thermal crystallization process on the first layer of aluminum oxide to form a first intermediate protective layer; forming a second layer of aluminum oxide, by atomic layer deposition, above the first intermediate protective layer; and performing a thermal crystallization process on the second layer of aluminum oxide to form a second intermediate protective layer and thereby completing the formation of the protective layer. The method for forming the protective layer can be used, for example, during the manufacturing steps of an inertial sensor such as a gyroscope or an accelerometer.

Abstract: A method for manufacturing a biosensor includes forming an electrode layer on a flexible foil. An adhesive layer is positioned on the foil layer, and a first photo-definable hydrogel membrane is positioned over the electrode layer and the adhesive layer. A second photo-definable hydrogel membrane with an immobilized bio-recognition element is positioned over the first hydrogel membrane in contact with the electrode layer through an opening in the first hydrogel membrane.

Abstract: Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.

Abstract: A process for manufacturing a packaged microelectromechanical device includes: forming a lid having a face and a cavity open on the face; coating the face of the lid and walls of the cavity with a metal layer containing copper; and coating the metal layer with a protective layer.

Abstract: A back-side illuminated pixel including a semiconductor substrate of a first conductivity type coated, on the front side of the pixel, with a three-layer assembly successively including a first layer of the second conductivity type, an insulating layer, and a second semiconductor layer. The three-layer assembly is interrupted in a central portion of the pixel by a transfer region of the first conductivity type laterally delimited by an insulated conductive wall extending from the front surface, Transistors are formed in the second semiconductor layer.

Abstract: An electrical check executed on wafer tests for the correct positioning or alignment of the probes of a probe card on the pads or bumps of the electronic devices integrated on the wafer. A signal is applied to cause a current to circulate in at least part of a seal ring of at least one of the electronic devices. In a case where the current flows between and through multiple electronic devices, the seal rings of those electronic devices are suitably interconnected to each other by electronic structures that extend through the scribe line between electronic devices.

Abstract: An electronic device having a functional portion and a test portion. The test portion includes a boundary scan register formed by a plurality of test cells arranged in the body according to a register sequence, where first test cells are configured to form a serial-to-parallel converter and second test cells are configured to form a parallel-to-serial converter. The test cells are each coupled to a respective data access pin of the device and to a respective input/output point of the functional part and have a first test input and a test output. The boundary scan register defines two test half-paths formed, respectively, by the first test cells and by the second test cells. The first test cells are directly coupled according to a first sub-sequence, and the second test cells are directly coupled according to a second sub-sequence.

Abstract: An overvoltage protection device protects a half bridge circuit that receives a supply voltage. The overvoltage protection device includes a high speed overvoltage detector that receives the supply voltage, detects whether an overvoltage situation is present, and outputs an overvoltage signal that disables the switches of the half bridge circuit before the switches can be damaged by the overvoltage situation. With both the switches of the half-bridge disabled, the entire supply voltage appears across the two switches in series, by which each switch only receives half the entire voltage. Thus, by quickly disabling both switches of the half-bridge each switch only needs a maximum voltage rating equal to half the maximum voltage rating of the half bridge circuit as a whole. This leads to reduced size and cost for the switches of the half-bridge circuit.

Abstract: A process for manufacturing surface-mount semiconductor devices, in particular of the Quad-Flat No-Leads Multi-Row type, comprising providing a metal leadframe, in particular a copper leadframe, which includes a plurality of pads, each of which is designed to receive the body of the device, the pads being separated from adjacent pads by one or more rows of wire-bonding contacting areas, outermost rows from among the one or more rows of wire-bonding contacting areas identifying, together with outermost rows corresponding to the adjacent pads, separation regions.

Abstract: The non-volatile memory device comprises memory cells each comprising a selectable state transistor having a floating gate and a control gate. The state transistor is of the depletion-mode type and is advantageously configured so as to have a threshold voltage that is preferably negative when the memory cell is in a virgin state. When the memory cell is read, a read voltage of zero may then be applied to the control gate and also to the control gates of the state transistors of all the memory cells of the memory device.

Abstract: Single gate and dual gate FinFET devices suitable for use in an SRAM memory array have respective fins, source regions, and drain regions that are formed from portions of a single, contiguous layer on the semiconductor substrate, so that STI is unnecessary. Pairs of FinFETs can be configured as dependent-gate devices wherein adjacent channels are controlled by a common gate, or as independent-gate devices wherein one channel is controlled by two gates. Metal interconnects coupling a plurality of the FinFET devices are made of a same material as the gate electrodes. Such structural and material commonalities help to reduce costs of manufacturing high-density memory arrays.

Abstract: An electronic device includes a support board having a mounting face and an integrated circuit chip mounted on the mounting face. An encapsulation block embeds the integrated circuit chip, the encapsulation block extending above the integrated circuit chip and around the integrated circuit chip on the mounting face of the support board. The encapsulation block includes a front face with a hole passing through the encapsulation block to uncovering at least part of an electrical contact. A layer made of an electrically conducting material fills the hole to make electrical connection to the electrical contact and further extends over the front face of the encapsulation block.

Abstract: A signal is protected against an attack by an enhancement process that checks the conformity of an actual state of the signal with respect to an expected state. A protective action is exercised on the signal if the actual state of the signal is not in conformity with the expected state, so as to neutralize or nullify said attack.

Abstract: An electronic device includes a carrier substrate with at least one electronic-circuit chip mounted on a front face of the carrier substrate. An encapsulation block on the front face and embedding the electronic-circuit chip has a periphery with corners. The encapsulating block further has, in at least one local zone located in at least one corner and from the front face of the carrier substrate, a smaller thickness than a thickness of the encapsulation block at least in a surrounding zone. The electronic device is manufactured by a process in which the zone of smaller thickness is obtained by molding or by machining.