Abstract: An AC/DC converter receives an AC voltage at a first terminal and a second terminal. A rectifying bridge has a first input terminal coupled via a resistive element to the first terminal and a second input terminal connected to the second terminal, with output terminals of the rectifying bridge coupled to third and fourth terminals of the converter for generating a DC voltage. A first controllable rectifying thyristor couples the first terminal to the third terminal and a second controllable rectifying thyristor couples the fourth terminal to the first terminal. The resistive element functions as an inrush protection device during a first phase when the thyristors are turned off. In a second phase, the thyristors are selectively actuated.

Abstract: A power switching converter includes a switch coupled to an input terminal through a primary winding of a transformer and a control circuit configured to drive the switch to provide a regulated output signal at a secondary winding of the transformer. A wake up circuit is provided to force the switching-on of the switch when the power converter enters in a burst mode. The wake up circuit includes a transmitting section coupled to the secondary winding and a receiving section coupled to an auxiliary winding of the transformer and the control circuit. The transmitting section is configured to provide a wake up signal communicated in a wireless manner to the receiving section when the output signal falls below a threshold value.

Abstract: A capacitive discharge circuit includes a line having a capacitance, a switched capacitor circuit including a capacitor, a switched circuit coupled to the line, and a voltage regulator coupled between the switched capacitor circuit and the switched circuit. A controller operates the switched capacitor circuit and switched circuit to in a first phase, charge the capacitor by coupling the capacitor between a common mode and a power supply, and in a second phase, discharge the capacitor by coupling the voltage regulator in series with the capacitor between the power supply node a ground. The controller is also configured to in a third phase, charge the capacitor by coupling the capacitor between the common mode and the power supply, and in a fourth phase, share charge between the line and the capacitor by coupling the voltage regulator and the capacitor in series between the line and the ground.

Abstract: A circuit is for controlling a power transistor of a DC/DC converter. The circuit may include first and second first transistors coupled in series between a first reference voltage and a control terminal of the power transistor, the first and second transistors defining a first junction node. The circuit may include third and fourth transistors coupled in series between the control terminal and a second reference voltage, the third and fourth transistors defining a second junction node. The first and second transistors may have a first conductivity type different from a second conductivity type of the third and fourth transistors. The circuit may include a capacitive element coupled between the first and second junction nodes.

Abstract: A method for fabricating an electronic device, and an electronic device in a stacked configuration, includes a rear face of an integrated-circuit chip that is fixed to a front face of a support wafer. A protective wafer is located facing and at a distance from the front face of the chip, and an infused adhesive is interposed between the chip and the protective wafer and located on a zone of the front face of the chip outside a central region of this front face. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. An obstruction barrier is arranged between the chip and the protective wafer and is disposed outside the central region of the front face of the chip. An encapsulation ring surrounds the chip, the protective wafer and the obstruction barrier.

Abstract: A switching regulator includes circuitry for reducing conductive emissions caused when the regulators switch from one transistor switch to the other. The switching regulator includes at least one switch with a diode connected from the source to the drain of at least one of the transistor switches. When the regulator switches from one transistor switch to the other, the circuitry initiates turning on the switch with a relatively small, current-limited signal, waits for the diode across the recently turned off switch to complete reverse recovery, and then quickly turns the new switch fully on.

Abstract: A method of fabrication, including the steps for supplying a substrate including a layer of semiconductor material covered by a sacrificial gate including a sacrificial gate insulator including a middle part, and edges covered by sacrificial spacers and having a thickness tox; removal of the sacrificial gate insulator and the sacrificial gate material; formation of a conformal deposition of thickness thk of dielectric material inside of the groove formed in order to form a gate insulator, with tox>thk?tox/2; formation of a gate electrode within the groove; removal of the sacrificial spacers so as to open up edges of the gate insulator layer; formation of spacers on the edges of the gate insulator layer on either side of the gate electrode, these spacers having a dielectric constant at the most equal to 3.5.

Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.

Abstract: A scan chain for testing a combinatorial logic circuit includes a first scan chain path of flip-flops connected to the combinatorial logic circuit for functional mode operation during runtime of the combinatorial logic circuit. A second scan chain path of flip-flops is also connected to the combinatorial logic circuit and supports both a shift mode and a capture mode. The second scan chain path operates in shift mode while the first scan chain path is connected to the combinatorial logic circuit for functional mode operation. The second scan chain is then connected to the combinatorial logic circuit when run time is interrupted and operates in capture mode to apply the test data to the combinatorial logic circuit.

Abstract: An electrical connector includes a frame delimiting an elongated open cavity, and having two parallel long sides provided with contact areas capable of cooperating with contact areas of a complementary electrical connector. Each long side is formed of a multilayer printed circuit board.

Abstract: A method for forming an electronic device includes embedding an integrated circuit die in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.

Abstract: An active stylus is capacitively coupled to a capacitive touch panel for communication. The active stylus operates in a wait mode to receive initial communications from the panel. In response to such receipt, the active stylus synchronizes to a repeating communications frame implementing time division multiplexing. Communications from the active stylus to the panel include: information communications; synchronization communications and communications specific for columns and/or rows of the panel. Communications from the panel to the active stylus may be addressed uniquely to the stylus or commonly to a group of styluses.

Abstract: A receiver is arranged to receive a plurality of Global Navigation Satellite System (GNSS) signals from up to four different satellite navigation systems including a GLONASS system, a BeiDou system, a GPS system, and a Galileo system. Received GNSS signals are mixed with a first local frequency signal to generate a plurality of mixed signals. The mixed signals are processed in up to three parallel branches. In a first branch, a first portion of the mixed signals are transformed by passing the first portion through a band-pass filter having a bandwidth between about 0 MHz and 46 MHz and by amplifying the filtered signals with an AGC circuit. In a second branch, a second portion of the mixed signals are transformed by rejecting image signals of the second portion with an image rejection filter and mixing image rejection filter output signals with a second local frequency signal to derive first remixed signals.

Abstract: A method is for aligning an electro-optic device. The method may include initially positioning an optical fiber array adjacent to optical grating couplers, and actively aligning the optical fiber array relative to the optical grating couplers in a yaw direction and a roll direction to determine a yaw and roll alignment at a first operating wavelength. The method may include actively aligning the optical fiber array relative to optical grating couplers in an x direction and a y direction to determine a first x and y alignment at the first operating wavelength, determining a second operating wavelength, and actively aligning the optical fiber array again relative to the optical grating couplers in the x direction and y direction to determine a second x and y alignment at the second operating wavelength.

Abstract: A proximity detector device may include a first interconnect layer including a first dielectric layer, and first electrically conductive traces carried thereby, an IC layer above the first interconnect layer and having an image sensor IC, and a light source IC laterally spaced from the image sensor IC. The proximity detector device may include a second interconnect layer above the IC layer and having a second dielectric layer, and second electrically conductive traces carried thereby. The second interconnect layer may have first and second openings therein respectively aligned with the image sensor IC and the light source IC. Each of the image sensor IC and the light source IC may be coupled to the first and second electrically conductive traces. The proximity detector device may include a lens assembly above the second interconnect layer and having first and second lenses respectively aligned with the first and second openings.

Abstract: One or more embodiments are directed to semiconductor packages, including stacked packages, with one or more cantilever pads. In one embodiment a recess is located in a substrate of the package facing the cantilever pad. The cantilever pad includes a conductive pad on which a conductive ball is formed. The cantilever pad is configured to absorb stresses acting on the package.

Abstract: An integrated magnetoresistive sensor of an AMR (Anisotropic Magneto Resistance) type, formed by a magnetoresistive strip of ferromagnetic material and having an elongated shape with a preferential magnetization direction. A set/reset coil has a stretch, which extends over and transversely to the magnetoresistive strip. A concentrating region, also of ferromagnetic material, extends over the stretch of the set/reset coil so as to form a magnetic circuit for the field generated by the set/reset coil during steps of refresh and maintenance of magnetization of the magnetoresistive coil.

Abstract: An apparatus for nucleic acid sequencing includes a nanochannel and a conveying device, configured to move a nucleic acid strand through the nanochannel. The conveying device includes: a first electrode, a second electrode, and a third electrode, which are arranged along the nanochannel so as to be in contact with a fluid occupying the nanochannel, the second electrode being arranged between the first electrode and the third electrode; and a control unit configured to apply a first voltage, a second voltage, and a third voltage, respectively, to the first electrode, the second electrode and the third electrode, for controlling movement of the nucleic acid strand through the nanochannel.

Abstract: A row decoder for a non-volatile memory device includes an input and pre-decoding module that receives address signals and generates pre-decoded address signals. A decoding module receives the pre-decoded address signals for generation on an output of decoded address signals. A driving module generates biasing signals for biasing wordlines of a memory array. The decoding module envisages a plurality of decoding stages, each of which carries out an operation of an OR logic combination between a first and a second predecoded address signal to be combined. The decoding module includes at least one first pass transistor for selectively transferring onto the output the one between the first and second predecoded address signals to be combined in a first operating condition. The decoding module includes at least one first pull-up transistor to selectively bring the output to a high state in at least one second operating condition.

Abstract: A pattern of symbols is generated and sent to a projector, wherein the pattern includes an array of symbols having a given number of symbol columns and symbol rows, and an image is obtained from a camera. Next the image is decoded in order to generate a decoded pattern of symbols and the depth map is generated as a function of the pattern and the decoded pattern. The image is decoded by placing an array of classification windows on the image and determining the displacement of each classification window in order to optimize a given cost function. Finally, the decoded pattern is generated by determining a respective symbol for each classification window.