Patents Assigned to STMicroelectronics AS
  • 3D video transmission on a legacy transport infrastructure
    Patent number: 9762886
    Abstract: The present disclosure relates to a method for transmitting two consecutive pairs of images. The method may include decimating each image with a ratio of 2, assembling the two decimated images of each pair in a composite image, transmitting the composite images, and reconstructing complete images from the composite images. In decimation, the information removed from the images of the first pair may be kept in the images of the second pair, from the spatial point of view, and the complete images may be reconstructed by de-interlacing processing from the composite images.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: September 12, 2017
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Frankie Eymard, Jean-Louis Labyre
  • Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures
    Patent number: 9761699
    Abstract: A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer; subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer; performing an annealing process so as to recrystallize the rSiGe layer; epitaxially growing a tensile strained silicon layer on the rSiGe layer; and patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: September 12, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.
    Inventors: Bruce B. Doris, Hong He, Junli Wang, Nicolas J. Loubet
  • Hybrid photonic and electronic integrated circuits
    Patent number: 9759861
    Abstract: A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths can be created substantially simultaneously in the same masking cycle. This is made possible by a disparity in the widths of the respective features, the optical signal paths being significantly wider than the electrical ones. Using a damascene process, the structures of disparate widths are plated with metal that over-fills narrow trenches and under-fills a wide trench. An optical cladding material can then be deposited into the trench so as to surround an optical core for light transmission.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: September 12, 2017
    Assignee: STMicroelectronics, Inc.
    Inventor: John H. Zhang
  • Method for making a shielded integrated circuit (IC) package with an electrically conductive polymer layer
    Patent number: 9761538
    Abstract: A method for making shielded integrated circuit (IC) packages includes providing spaced apart IC dies carried by a substrate and covered by a common encapsulating material, and cutting through the common encapsulating material between adjacent IC dies to define spaced apart IC packages carried by the substrate. An electrically conductive layer is positioned over the spaced apart IC packages and fills spaces between adjacent IC packages. The method further includes cutting through the electrically conductive layer between adjacent IC packages and through the substrate to form the shielded IC packages.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: September 12, 2017
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Rennier Rodriguez, Frederick Arellano, Aiza Marie Agudon
  • Serial transmission having a low level EMI
    Patent number: 9762383
    Abstract: A method for transmitting data in series includes producing a scrambled signal by applying a scrambling using a pseudo-random sequence to an incoming serial signal conveying the data and producing an outgoing serial signal. The scrambled signal is monitored to detect occurrences of one or more data patterns. In response to the detection of one or more occurrences, one or more actions are taken to protect data in the output signal.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: September 12, 2017
    Assignees: STMICROELECTRONICS (GRENOBLE 2) SAS, STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Julien Saade, Abdelaziz Goulahsen
  • Reconfigurable sense amplifier for a memory device
    Patent number: 9761316
    Abstract: A memory sense amplifier is configurable on command between a current-sensing mode and a voltage-sensing mode. The sense amplifier is intended, in its current-sensing configuration, to read a datum stored in a memory cell connected to the amplifier, and is intended, in its voltage-sensing configuration, to read a datum stored in a bit-line latch connected to the amplifier.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: September 12, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: François Tailliet, Victorien Brecte
  • PROCESS FOR FORMING A LAYER OF EQUIAXED TITANIUM NITRIDE AND A MOSFET DEVICE HAVING A METAL GATE ELECTRODE INCLUDING A LAYER OF EQUIAXED TITANIUM NITRIDE
    Publication number: 20170256625
    Abstract: Local variability of the grain size of work function metal, as well as its crystal orientation, induces a variable work function and local variability of transistor threshold voltage. If the metal nitride for the work function metal of the transistor gate is deposited using a radio frequency physical vapor deposition, equiaxed grains are produced. The substantially equiaxed structure for the metal nitride work function metal layer (such as with TiN) reduces local variability in threshold voltage.
    Type: Application
    Filed: May 22, 2017
    Publication date: September 7, 2017
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Pierre Caubet, Florian Domengie, Carlos Augusto Suarez Segovia, Aurelie Bajolet, Onintza Ros Bengoechea
  • OPTICAL ELECTRONIC DEVICE AND METHOD OF FABRICATION
    Publication number: 20170256514
    Abstract: Electronic devices are collectively fabricated from a main wafer which includes optical elements and a secondary wafer that are mounted one on top of the other to form a combined wafer. A mounting face of the secondary wafer is mated to a front face of the main wafer in such a manner that recesses within the mounting face of the secondary wafer are aligned over the optical elements. The thickness of the secondary wafer reduced until the recesses are opened to form ring structures with openings at the recesses. The combined wafer is diced to form electronic devices. A base wafer of the main wafer and the secondary wafer are made of a same semiconductor material (for example, silicon).
    Type: Application
    Filed: August 17, 2016
    Publication date: September 7, 2017
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventor: Eric Saugier
  • Vacuum integrated electronic device and manufacturing process thereof
    Patent number: 9754756
    Abstract: A vacuum integrated electronic device has an anode region of conductive material; an insulating region on top of the anode region; a cavity extending through the insulating region and having a sidewall; and a cathode region. The cathode region has a tip portion extending peripherally within the cavity, adjacent to the sidewall of the cavity. The cathode region is formed by tilted deposition, carried out at an angle of 30-60° with respect to a perpendicular to the surface of device.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: September 5, 2017
    Assignees: STMicroelectronics S.r.l., STMicroelectronics Pte Ltd
    Inventors: Davide Giuseppe Patti, Myung Sung Kim
  • Communication on an I2C bus
    Patent number: 9753886
    Abstract: A communication system includes an I2C bus interconnecting at least one first device and one second device. At least one direct data link, other than the I2C bus, interconnects the first and second devices. The system is configurable to operate in: a first operating mode providing for data only transmission between the first and second devices over the I2C bus; and a second operating mode providing for simultaneous data transmission between the first and second devices over both the I2C bus and said data link.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: September 5, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Francois Tailliet
  • Electrostatically actuated oscillating structure with oscillation starting phase control, and manufacturing and driving method thereof
    Patent number: 9753279
    Abstract: An electrostatically actuated oscillating structure includes a first stator subregion, a second stator subregion, a first rotor subregion and a second rotor subregion. Torsional elastic elements mounted to the first and second rotor subregions define an axis of rotation. A mobile element is coupled to the torsional elastic elements. The stator subregions are electrostatically coupled to respective regions of actuation on the mobile element. The stator subregions exhibit an element of structural asymmetry such that the electrostatic coupling surface between the first stator subregion and the first actuation region differs from the electrostatic coupling surface between the second stator subregion and the second actuation region.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: September 5, 2017
    Assignees: STMicroelectronics S.R.L., STMicroelectronics International N.V.
    Inventors: Benedetto Vigna, Marco Ferrera, Sonia Costantini, Marco Salina
  • Microelectromechanical sensing structure for a pressure sensor including a deformable test structure
    Patent number: 9752944
    Abstract: A microelectromechanical sensing structure having a membrane region including a membrane that undergoes deformation as a function of a pressure and a first actuator that is controlled in a first operating mode and a second operating mode, the first actuator being such that, when it operates in the second operating mode, it contacts the membrane region and deforms the membrane in a way different from when it operates in the first operating mode.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: September 5, 2017
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Alberto Pagani
  • Method of operating an integrated switchable capacitive device
    Patent number: 9754934
    Abstract: A variable capacitor includes a fixed main capacitor electrode disposed in a first metal layer overlying a substrate, a second main capacitor electrode spaced from the fixed main capacitor electrode, and a movable capacitor electrode disposed in the first metal layer adjacent the fixed main capacitor electrode. The movable capacitor electrode can be caused to be in a first position ohmically electrically connected to the fixed main capacitor electrode such that the variable capacitor has a first capacitance value or in a second position spaced from the fixed main capacitor electrode such that the variable capacitor has a second capacitance value.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: September 5, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Single stage cascoded voltage level shifting circuit
    Patent number: 9755621
    Abstract: A level shifting circuit operates at a high voltage level without stressing the transistors. The circuit has the ability to swing between large supply domains. Multiple output voltage levels are supported for the level shifted signal. Additionally, output nodes are stably driven to supply voltage levels that do not vary with respect to process corner and temperature.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: September 5, 2017
    Assignee: STMicroelectronics International N.V.
    Inventors: Rohan Sinha, Vikas Rana
  • Embedded shape sige for strained channel transistors
    Patent number: 9755051
    Abstract: An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress into the channel regions of the NMOS transistors and compressive stress into the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: September 5, 2017
    Assignee: STMicroelectronics, Inc.
    Inventors: John H. Zhang, Pietro Montanini
  • AC-DC converter with inrush current limitation
    Patent number: 9755541
    Abstract: An AC/DC converter includes: a first terminal and a second terminal for receiving an AC voltage and a third terminal and a fourth terminal for supplying a DC voltage. A rectifying bridge includes input terminals respectively coupled to the first terminal and the second terminal, and output terminals respectively coupled to the third terminal and fourth terminal. A first branch of the rectifying bridge includes, connected between the output terminals, two series-connected thyristors with a junction point of the two thyristors being connected to a first one of the input terminals. A second branch of the rectifying bridge is formed by series connected diodes. A control circuit is configured to generate control signals for application to the control gates of the thyristors.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: September 5, 2017
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Laurent Gonthier, Muriel Nina, Romain Pichon
  • Electronic device provided with an integrated conductor element and fabrication method
    Patent number: 9754851
    Abstract: An electronic device includes a support plate having a mounting face and an electrical connection network. An integrated circuit chip is mounted on the mounting face and linked to the electrical connection network. An en encapsulation block embeds the integrated circuit chip. An additional element made of an electrically conductive material is at least partly embedded within the encapsulation block. The additional conductive element has a main portion extending parallel to the support plate and has a secondary portion that is linked electrically to the integrated circuit chip. An opening is formed in the encapsulation block, and the secondary portion extends into that opening to make the electrical link. The additional conductive element may be an antenna.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: September 5, 2017
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: David Auchere, Laurent Marechal, Yvon Imbs, Laurent Schwarz
  • Hardware monitor with context switching and selection based on a data memory access and for raising an interrupt when a memory access address is outside of an address range of the selected context
    Patent number: 9753870
    Abstract: A monitor includes a register configured to store at least two contexts and a context change value. A context selector is configured to select at least one of the two contexts for context monitoring. The selection is made dependent on whether the context change value matches a first part of a memory access address.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: September 5, 2017
    Assignee: STMicroelectronics (Research & Development) Limited
    Inventors: Mark Trimmer, Paul Elliott
  • Apparatus with device with fault detection protection
    Patent number: 9753060
    Abstract: A device such as a laser diode is provided with a monitoring arrangement. The monitoring arrangement has voltage to current converters arranged to provide respectively currents which are proportional to the respective voltages on an anode and on a cathode of the laser diode. The monitoring arrangement provides a first output signal when the laser diode is on too long. That output signal is used to cause the laser diode to be switched off.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: September 5, 2017
    Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventor: Shatabda Saha
  • Trench epitaxial growth for a FinFET device having reduced capacitance
    Patent number: 9755031
    Abstract: A FinFET device includes a semiconductor fin, a gate electrode extending over a channel of the fin and sidewall spacers on each side of the gate electrode. A dielectric material is positioned on each side of a bottom portion of said fin, with an oxide material on each side of the fin overlying the dielectric material. A recessed region, formed in the fin on each side of the channel region, is delimited by the oxide material. A raised source region fills the recessed region and extends from the fin on a first side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer. A raised drain region fills the recessed region and extends from the fin on a second side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: September 5, 2017
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation, GlobalFoundries Inc.
    Inventors: Qing Liu, Xiuyu Cai, Ruilong Xie, Chun-Chen Yeh