Abstract: An array of image sensing elements is arranged in rows and columns. A readout circuit for each column includes a circuit configured to receive a column select signal. A memory stores data indicative of a voltage of an image sensing element which is being read. An analog to digital conversion circuit provides an output to the memory to control the storing of data. The output is dependent on the voltage of the image sensing element. Power control circuitry operates to disable, at least partially, the analog to digital conversion circuit when the column has not been selected.

Abstract: A memory device of the non-volatile electrically-erasable and programmable memory type is provided. The memory device includes a matrix memory plane of memory cells connected to bit lines. Programming circuitry is configured to select a memory cell and to apply a programming pulse to the corresponding bit line. The memory plane is disposed in a local well at a floating potential and the programming circuitry is configured to increase the potential of the local well simultaneously with the application of the programming pulse to the bit line of a selected memory cell.

Abstract: Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode.

Abstract: A method of making an inkjet print head may include forming, by sawing with a rotary saw blade, continuous slotted recesses in a first surface of a wafer. The continuous slotted recesses may be arranged in parallel, spaced apart relation, and each continuous slotted recess may extend continuously across the first surface. The method may further include forming discontinuous slotted recesses in a second surface of the wafer to be aligned and coupled in communication with the continuous slotted recesses to define alternating through-wafer channels and slotted recess portions. The method may further include selectively filling the residual slotted recess portions to define through-wafer ink channels.

Abstract: In one embodiment a UHF RFID reader is adapted to operate in either a reader mode or in a tag emulation mode, wherein in the reader mode the UHF RFID reader communicates with at least one RFID tag to access the at least one tag's memory contents and in the tag emulation mode the UHF RFID reader communicates with at least one other UHF RFID reader to share memory content with the at least one other UHF RFID reader. Furthermore, an RFID network and a method for communication in an RFID network are described.

Abstract: An electronic device includes an integrated circuit with a MOS transistor and a heating circuit electrically coupled to at least two points of one of the source or drain semiconductive region of the transistor. A portion of the source or drain semiconductive region between the two points forms a resistive element. The heating circuit is configured to cause a current to circulate through the resistive element between the two points to heat an active region of the transistor.

Abstract: A level shifter circuit is configured to receive first and second complementary input signals. Each of the first and second complementary input signals have a value of either a first supply voltage or a first reference voltage. The level shifter further includes a strong latch circuit operable in response to the first and second complementary input signals to drive one of first and second output signals to a second supply voltage and includes a weak latch circuit operable to drive the other of the first and second output signals to a second reference voltage.

Abstract: A stand-alone DC power network is provided with a DC to DC power converter only, and does not have a converter that will convert AC to DC. In addition, each of the different terminals that provides the DC voltage at different levels will be ranked according to priority as to which ones are the most important to supply the full voltage to, and which ones are of secondary importance in the event there is insufficient power in the system to provide full voltage at the specified current for the different loads. A processor monitors the voltage and current at each of the terminals, and in the event a current is attempted to be drawn from the system which would cause a first priority terminal to be reduced in voltage, the processor will instead reduce the power provided to the second priority terminal and ensure that the first priority terminal does not have a significant reduction in the specified voltage or the amount of current supplied to that terminal at the specified voltage.

Abstract: A fluid ejection device, comprising: a first semiconductor body including an actuator, which is operatively coupled to a chamber for containing the fluid and is configured to cause ejection of the fluid; and a channel for inlet of the fluid, which extends in a first direction and has a section having a first dimension; and a second semiconductor body, which is coupled to the first semiconductor body and has an ejection nozzle configured to expel the fluid. The second semiconductor body further comprises a first restriction channel, which is fluidically coupled to the inlet channel, extends in a second direction orthogonal to the first direction and has a respective section with a second dimension smaller than the first dimension so as to form a restriction between the inlet channel and the chamber.

Abstract: It is described an integrated gas sensor device comprising a silicon substrate and an oxide layer on the silicon substrate, as well as a working electrode, a counter electrode and a reference electrode, on the oxide layer, the working electrode and the counter electrode having respective active area exposed to an environmental air through at least a plurality of first openings and a plurality of second openings in the oxide layer in correspondence of the working electrode and of the counter electrode, further comprising an electrolyte layer portion and a hydrogel layer portion on the electrolyte layer portion, the electrolyte and hydrogel layer portions having a same size, suitable to cover at least the working, counter and reference electrodes, the hydrogel layer portion acting as a “quasi solid state” water reservoir.

Abstract: A radiation-hardened logic device includes a first n-channel transistor coupled by its main conducting nodes between an output node of a logic device and a supply voltage rail and a first p-channel transistor coupled by its main conducting nodes between the output node of the logic device and a ground voltage rail. The gates of the first n-channel and p-channel transistors are coupled to the output node.

Abstract: A switching device including: a body of semiconductor material, which has a first conductivity type and is delimited by a front surface; a contact layer of a first conductive material, which extends in contact with the front surface; and a plurality of buried regions, which have a second conductivity type and are arranged within the semiconductor body, at a distance from the contact layer.

Abstract: A bipolar transistor is supported by a substrate including a semiconductor layer overlying an insulating layer. A transistor base is formed by a base region in the semiconductor layer that is doped with a first conductivity type dopant at a first dopant concentration. The transistor emitter and collector are formed by regions doped with a second conductivity type dopant and located adjacent opposite sides of the base region. An extrinsic base includes an epitaxial semiconductor layer in contact with a top surface of the base region. The epitaxial semiconductor layer is doped with the first conductivity type dopant at a second dopant concentration greater than the first dopant concentration. Sidewall spacers on each side of the extrinsic base include an oxide liner on a side of the epitaxial semiconductor layer and the top surface of the base region.

Abstract: A source image is transformed into a destination image having a target aspect ratio. A reference region in the source image is defined. An extended region of interest of the source image having the target aspect ratio and containing the reference region is defined. A set of candidate image regions of increasing resolutions from the extended region of interest is determined, each having the target aspect ratio and containing the reference region. Candidate image regions are scaled to form a candidate target images. A quality metric is used to select a target image providing the best quality metric value.

Abstract: An electronic device may include system and serial peripheral interface (SPI) clocks, and a host interface each switchable between active and inactive states, a serial controller coupled to the system clock, and a memory. A slave controller may generate a request active signal based upon a transaction request from a host and causing each of the system clock, SPI clock, and host interface into the active state, store request data in the memory, and switch the host interface to the inactive state based upon the request data being stored. The serial controller may process the request based upon the request active signal, and generate a request complete signal based upon the request being processed. The slave controller may switch the system clock to the inactive state based upon the request complete signal. The SPI clock may be switched to the inactive state based upon the request complete signal.

Abstract: A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wraparound gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.

Abstract: The thinning of a semiconductor substrate of an integrated circuit from a back face is detected using the measurement of a physical quantity representative of the resistance between the ends of two electrically-conducting contacts situated at an interface between an insulating region and an underlying substrate region. The two electrically-conducting contacts extend through the insulating region to reach the underlying substrate region.

Abstract: Upstream burst transmit times are dynamically communicated to the transmit unit in grants issued over time and in any order. A critical parameter is when to trigger the operation to order the buffered data stream for transmission. If the ordering operation is triggered too soon, a later grant of an earlier burst transmit time may not be accounted for and the subsequent transmission could violate the transmission order rule. If the ordering operation is triggered too late, the decision to transmit a burst at an earlier burst transmit time may violate the margin rule. To address these concerns, a fetch offset time in advance of each granted burst transmit time is assigned. As each fetch offset time is sequentially reached, a next partial data portion of the buffered data stream is prepared for burst communication.

Abstract: A circuit for comparing a voltage with a threshold, including: first and second nodes of application of the voltage; a first branch including a first transistor series-connected with a first resistor between first and second nodes; a second branch parallel to the first branch, including second and third series-connected resistors forming a voltage dividing bridge between the first and second nodes, the midpoint of the dividing bridge being connected to a control node of the first transistor; and a third branch including a second transistor in series with a resistive and/or capacitive element, between the control node of the first transistor and the first or second node, a control node of the second transistor being connected to the junction point of the first transistor and of the first resistor.

Abstract: A voltage regulator is controlled to improve supply voltage rejection by cancelling an alternating component of a supply voltage signal that is capacitively coupled to a high-impedance node within the voltage regulator. This cancellation is done by capacitively coupling an inverted version of the alternating component to the high-impedance node to thereby substantially cancel the alternating component present on the high-impedance node. The high-impedance node may be a high-impedance voltage reference node of the voltage regulator.