Patents Assigned to STMicroelectronics (Crolles 2)
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Patent number: 11817377Abstract: A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.Type: GrantFiled: August 1, 2022Date of Patent: November 14, 2023Assignee: STMicroelectronics (Grenoble 2) SASInventors: Romain Coffy, Fabien Quercia
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Patent number: 11817791Abstract: A synchronous rectifier driver circuit is configured to drive a synchronous rectifier FET and includes a first terminal configured to be connected to a source terminal of the synchronous rectifier FET. A second terminal is configured to be connected to a drain terminal of the synchronous rectifier FET, and a third terminal is configured to be connected to a gate terminal of the synchronous rectifier FET. The synchronous rectifier driver circuit is configured to measure the voltage between the second terminal and the first terminal, and detect a switch-on instant in which the measured voltage reaches a first threshold value and a switch-off instant in which the measured voltage reaches a second threshold value. The synchronous rectifier driver circuit generates a drive signal between the third terminal and the first terminal as a function of the measured voltage.Type: GrantFiled: September 30, 2021Date of Patent: November 14, 2023Assignees: STMicroelectronics S.r.l., STMicroelectronics Design and Application S.R.O.Inventors: Alberto Iorio, Maurizio Foresta, Emilio Volpi, Jan Novotny
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Patent number: 11816290Abstract: System for detecting a touch gesture of a user on a detection surface, comprising: a processing unit; and an accelerometer to detect a vibration at the detection surface and generate a vibration signal. The processing unit is configured to: acquire the vibration signal, detect, in the vibration signal, a signal characteristic which can be correlated to the touch gesture of the user, detect, in the vibration signal, a stationarity condition preceding and/or following the detected signal characteristic, and validate the touch gesture in the event that both the signal characteristic and the stationarity condition have been detected. An electrostatic charge sensor may also be used as a further parameter to validate the touch gesture.Type: GrantFiled: November 15, 2022Date of Patent: November 14, 2023Assignee: STMICROELECTRONICS S.r.l.Inventors: Federico Rizzardini, Lorenzo Bracco
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Patent number: 11816288Abstract: A method includes: displaying, an image on a display by sequentially displaying a plurality of frames of the image, the plurality of frames including a first frame and second frame; performing a first noise sampling scan at a plurality of frequencies at a first time location within a first frame; determining a first frequency from the plurality of frequencies with the lowest noise; performing a first mutual sensing scan at the first frequency; performing, a second noise sampling scan at the plurality of frequencies at a second time location within a second frame of the plurality of frames, the second time location being a different frame location than the first time location; determining a second frequency from the plurality of frequencies with the lowest noise, the second frequency being different from the first frequency; and performing, a second mutual sensing scan at the second frequency.Type: GrantFiled: April 18, 2022Date of Patent: November 14, 2023Assignee: STMicroelectronics Asia Pacific Pte Ltd.Inventors: MooKyung Kang, Sang Hoon Jeon
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Patent number: 11818901Abstract: The disclosure relates to integrated circuits and methods including one or more rows of transistors. In an embodiment, an integrated circuit includes a row of bipolar transistors including a plurality of first conduction regions, a second conduction region, and a common base between the first conduction regions and the second conduction region. An insulating trench is in contact with each bipolar transistor of the row of bipolar transistors. A conductive layer is on the insulating trench and the common base between the first conduction regions. A spacer layer is between the conductive layer and the first conduction regions.Type: GrantFiled: September 29, 2021Date of Patent: November 14, 2023Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SASInventors: Philippe Boivin, Jean Jacques Fagot, Emmanuel Petitprez, Emeline Souchier, Olivier Weber
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Patent number: 11815628Abstract: An apparatus comprises an array of vertical-cavity surface-emitting lasers. Each of the vertical-cavity surface-emitting lasers is configured to be a source of light. The apparatus also comprises an optical arrangement configured to receive light from a plurality of the vertical-cavity surface-emitting lasers and to output a plurality of light beams.Type: GrantFiled: January 23, 2023Date of Patent: November 14, 2023Assignee: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITEDInventors: Christopher Townsend, Thineshwaran Gopal Krishnan, James Peter Drummond Downing, Kevin Channon
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Patent number: 11815547Abstract: A test circuit and a method for testing an integrated circuit are provided. The integrated circuit includes a test circuit. The test circuit includes a conductive track extending over at least a portion of the periphery of the integrated circuit, at least one component and an activation circuit adapted to deviating an input data signal into the conductive track during a test mode, and to transmitting the input data signal to the at least one component during a normal operating mode.Type: GrantFiled: September 7, 2021Date of Patent: November 14, 2023Assignee: STMICROELECTRONICS (ROUSSET) SASInventor: Francois Tailliet
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Patent number: 11817484Abstract: A method for manufacturing an electronic device includes locally implanting ionic species into a first region of a silicon nitride layer and into a first region of an electrically insulating layer located under the first region of the silicon nitride layer. A second region of the silicon nitride layer and a region of the electrically insulating layer located under the second region of the silicon nitride layer are protected from the implantation. The electrically insulating layer is disposed between a semi-conducting substrate and the silicon nitride layer. At least one trench is formed extending into the semi-conducting substrate through the silicon nitride layer and the electrically insulating layer. The trench separates the first region from the second region of the electrically insulating layer. The electrically insulating layer is selectively etched, and the etch rate of the electrically insulating layer in the first region is greater than the etch rate in the second region.Type: GrantFiled: September 27, 2022Date of Patent: November 14, 2023Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (ROUSSET) SASInventors: Franck Julien, Stephan Niel, Leo Gave
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Patent number: 11815568Abstract: An electronic device includes a magnetometer that outputs magnetometer sensor signals and a gyroscope that outputs gyroscope sensor signals. The electronic device includes a magnetometer calibration module that calibrates the magnetometer utilizing the gyroscope sensor signals. The electronic device generates a first magnetometer calibration parameter based on a Kalman filter process. The electronic device generates a second magnetometer calibration parameter based on a least squares estimation process.Type: GrantFiled: December 28, 2020Date of Patent: November 14, 2023Assignee: STMicroelectronics, Inc.Inventors: Mahaveer Jain, Mahesh Chowdhary
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Patent number: 11817838Abstract: An electronic amplification-interface circuit includes a differential-current reading circuit having a first input terminal and a second input terminal. The differential-current reading circuit includes a continuous-time sigma-delta conversion circuit formed by an integrator-and-adder module generating an output signal that is coupled to an input of a multilevel-quantizer circuit configured to output a multilevel quantized signal. The integrator-and-adder module includes a differential current-integrator circuit configured to output a voltage proportional to an integral of a difference between currents received at the first and second input terminals. A digital-to-analog converter, driven by a respective reference current, receives and converts the multilevel quantized signal into a differential analog feedback signal. The integrator-and-adder module adds the differential analog feedback signal to the differential signal formed at the first and second input terminals.Type: GrantFiled: March 4, 2022Date of Patent: November 14, 2023Assignee: STMicroelectronics S.r.l.Inventors: Calogero Marco Ippolito, Michele Vaiana
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Patent number: 11816466Abstract: An embodiment electronic device includes a memory containing a plurality of copies of firmware of the device.Type: GrantFiled: July 22, 2020Date of Patent: November 14, 2023Assignee: STMICROELECTRONICS (GRAND OUEST) SASInventor: Fabien Arrive
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Patent number: 11817864Abstract: In an embodiment a timing system includes a master timing device including a master oscillator stage configured to receive a reference signal and to generate a first main clock signal frequency-locked with the reference signal, a master timing stage including a master counter configured to update value with a timing that depends on the first main clock signal, the master timing stage configured to generate a first local clock signal of a pulsed type, a timing of pulses of the first local clock signal being controllable by the master counter and a master synchronization stage configured to generate a synchronization signal synchronous with the first local clock signal, wherein the synchronization signal includes a corresponding pulse for each group of consecutive pulses of the first local clock signal formed by a number (N) of pulses, and a slave timing device including a slave oscillator stage configured to receive the reference signal and to generate a second main clock signal frequency-locked with the referType: GrantFiled: June 14, 2022Date of Patent: November 14, 2023Assignee: STMicroelectronics S.r.l.Inventors: Luigi Sole, Antonio Giordano
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Publication number: 20230356999Abstract: A microelectromechanical device includes a support structure, a microelectromechanical system die, incorporating a microstructure and a connection structure between the microelectromechanical system die and the support structure. The connection structure includes a spacer structure, joined to the support structure, and a film applied to one face of the spacer structure opposite to the support structure. The spacer structure laterally delimits at least in part a cavity and the film extends on the cavity, at a distance from the support structure. The microelectromechanical system die is joined to the film on the cavity.Type: ApplicationFiled: April 27, 2023Publication date: November 9, 2023Applicant: STMICROELECTRONICS S.r.l.Inventors: Filippo DANIELE, Lorenzo BALDO, Davide MAERNA, Enri DUQI
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Publication number: 20230358541Abstract: A device including microelectromechanical systems (MEMS) sensors are used in dead reckoning in conditions where Global Positioning System (GPS) signals or Global Navigation Satellite System (GNSS) signals are lost. The device is capable of tracking the location of the device after the GPS/GNSS signals are lost by using MEMS sensors such as accelerometers and gyroscopes. By calculating a misalignment angle between a forward axis of a sensor frame of the device and a forward axis of a vehicle frame using the data received from the MEMS sensors, the device can accurately calculate the location of a user or the vehicle of the device even without the GPS/GNSS signals. Accordingly, a device capable of tracking the location of the user riding in the vehicle in GPS/GNSS signals absent environment can be provided.Type: ApplicationFiled: July 14, 2023Publication date: November 9, 2023Applicants: STMICROELECTRONICS, INC., STMICROELECTRONICS S.r.l.Inventors: Mahaveer JAIN, Mahesh CHOWDHARY, Roberto MURA, Nicola Matteo PALELLA, Leonardo COLOMBO
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Publication number: 20230358806Abstract: The disclosure relates to a scan chain circuit comprising cascaded flip-flops having a functional input node and a test input node configured to be selectively coupled to logic circuitry at a clock edge time. A clock line is provided configured to distribute one or more clock signals to the flip-flops in the chain, wherein the flip-flops in the chain have active clock edges applied thereto at respective clock edge times. The chain of flip-flops comprise a set of flip-flops configured to receive an edge inversion signal and to selectively invert their active clock edges in response to the edge inversion signal being asserted.Type: ApplicationFiled: July 18, 2023Publication date: November 9, 2023Applicant: STMICROELECTRONICS S.r.l.Inventor: Marco CASARSA
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Publication number: 20230361241Abstract: An optoelectronic device is manufactured by an epitaxial growth, on each first layer of many first layers spaced apart from each other on a first support, wherein the first is made of a first semiconductor material, of a second layer made of a second semiconductor material. A further epitaxial growth is made on each second layer of a stack of semiconductor layers. Each stack includes a third layer made of a third semiconductor material in physical contact with the second layer. Each stack is then separated from the first layer by removing the second layer using an etching that is selective simultaneously over both the first and third semiconductor materials. Each stack is then transferred onto a second support. Each of the first and third semiconductor materials is one of a III-V compound or a II-VI compound.Type: ApplicationFiled: April 27, 2023Publication date: November 9, 2023Applicant: STMicroelectronics (Crolles 2) SASInventor: Francois ROY
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Publication number: 20230361010Abstract: A semiconductor chip or die is arranged on a first surface of a thermally conductive die pad of a substrate such as a leadframe. An encapsulation of insulating material in molded onto the die pad having the semiconductor die arranged on the first surface. At the second surface of the die pad, opposite the first surface, the encapsulation borders on the die pad at a borderline around the die pad. A recessed portion of the encapsulation is provided, for example, via laser ablation, at the borderline around the die pad. Thermally conductive material such as metal material is filled in the recessed portion of the encapsulation around the die pad. The surface area of the thermally conductive die pad is augmented by the filling of thermally conductive material in the recessed portion of the encapsulation thus improving thermal performance of the device.Type: ApplicationFiled: April 27, 2023Publication date: November 9, 2023Applicant: STMicroelectronics S.r.l.Inventor: Riccardo VILLA
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Publication number: 20230361064Abstract: The present description relates to a method of manufacturing an end of an interconnection structure of an integrated circuit, the method including: providing an integrated circuit including an interconnection structure including copper interconnection elements at least partly extending through an insulating layer and flush with a first surface of said interconnection structure; forming a protection layer on the first surface of the interconnection structure, said protection layer including a material adapted to protecting the copper of the interconnection elements; forming a passivation layer on the protection layer, the passivation layer having a first thickness; and forming a first opening in the passivation layer across a second thickness smaller than the first thickness, to keep a residual passivation layer at the bottom of the first opening.Type: ApplicationFiled: May 3, 2023Publication date: November 9, 2023Applicant: STMicroelectronics (Crolles 2) SASInventors: Marion CROISY, Sylvie DEL MEDICO
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Publication number: 20230359262Abstract: The present disclosure is directed to a device configured to detect whether the device is in a bag or being taken out of the bag. The device determines whether the device is in a bag or being taken out of the bag based on motion measurements generated by a motion sensor and electrostatic charge measurements generated by an electrostatic charge sensor. By using both distance measurements and motion measurements, the device is able to detect whether the device is in the bag or being taken out of the bag with high efficiency, accuracy, and robustness.Type: ApplicationFiled: July 21, 2023Publication date: November 9, 2023Applicant: STMICROELECTRONICS S.r.l.Inventors: Stefano Paolo RIVOLTA, Roberto MURA, Marco BIANCO
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Publication number: 20230360927Abstract: A semiconductor integrated circuit chip is arranged on a first surface of a substrate that includes electrically conductive lead formations in an array, wherein the electrically conductive lead formations are covered by a masking layer at a second surface opposite the first surface. The semiconductor integrated circuit chip is electrically coupled to electrically conductive lead formations and an insulating encapsulation is molded on the semiconductor integrated circuit chip. The masking layer is then selectively removed, for example, via laser ablation, from one or more of the electrically conductive lead formations. The electrically conductive lead formations that are left uncovered by the masking layer are then removed by an etching process applied to the second surface of the substrate. The selective removal of the unmasked electrically conductive lead formations serves to increase a creepage distance between those conductive lead formations that are left in place.Type: ApplicationFiled: April 27, 2023Publication date: November 9, 2023Applicant: STMicroelectronics S.r.l.Inventor: Fulvio Vittorio FONTANA