Abstract: A sensor circuit for a power FET monitors current flowing through the FET and includes a regulator circuit regulating a first current flowing through a sense resistance, so voltage drop at the sense resistance corresponds to voltage drop between terminals of the FET. A measurement circuit provides a second current corresponding (or being proportional) to the first current. A first switch selectively applies the second current to a resistor based on a first control signal, and a low pass filter generates a low-pass filtered signal by filtering voltage at the resistor. A voltage follower generates a replica of the low-pass filtered signal, and a second switch selectively applies the replica to the resistor. When the FET is closed, a control circuit closes the first switch and opens the second electronic switch. When the FET is opened, the control circuit opens the first electronic switch and closes the second electronic switch.

Abstract: A method of operating a radar sensor system includes: frequency down-converting a reception signal that is chirp-modulated with a sequence of chirp ramps to an intermediate frequency signal; and high-pass filtering the intermediate frequency signal to produce a high-pass filtered signal. High-pass filtering includes: first high-pass filtering, with a first corner frequency, the intermediate frequency signal at each chirp in the chirp modulation of the reception signal; and replacing the first high-pass filtering with a second high-pass filtering with a second corner frequency, the first corner frequency being higher than the second corner frequency.

Abstract: A monolithic component includes a field-effect power transistor and at least one first Schottky diode inside and on top of a gallium nitride substrate.

Abstract: A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.

Abstract: System, method, and circuitry for simulating a memory architecture to generate a bin image of a file tree for a memory embedded on a programmable computing device. A memory configuration of the memory and a file tree identifying a file structure to be used in the memory are obtained. A bin image of a file system for the memory is generated based on the memory configuration and the file tree using a memory simulator and a file-management-system manager. The bin image is provided to the programmable computing device for storage in the memory.

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.

Abstract: The present description concerns a manufacturing method comprising the following steps: providing a silicon substrate having a via penetrating into the substrate from its front surface and comprising a silicon conductive core and a silicon oxide insulating sheath; etching the substrate from its rear surface, selectively over the sheath so that a portion of said at least one via protrudes from the rear surface; depositing a silicon oxide insulating layer on the rear surface; polishing the insulating layer to expose the core while leaving in place a portion of the thickness of the insulating layer; and forming a conductive electrode in contact with the core.

Abstract: A field effect transistor has a semiconductor layer with a top surface extending in a horizontal plane, and an active area defined in which are trench gate regions, which extend in depth with respect to the top surface and have an insulating coating layer and a conductive inner layer, and source regions, adjacent to the trench gate regions so as to form a conductive channel extending vertically. The trench gate regions have a plurality of first gate regions, which extend in length in the form of stripes through the active area along a first direction of the horizontal plane, and moreover a plurality of second gate regions, which extend in length in the form of stripes through the same active area along a second direction of the horizontal plane, orthogonal to, and crossing, the first gate regions. In particular, the first gate regions and second gate regions cross in the active area, joining with a non-zero curvature radius.

Abstract: MEMS structure, comprising: a semiconductor body; a cavity buried in the semiconductor body; a membrane suspended on the cavity; and at least one antistiction bump completely contained in the cavity with the function of preventing the side of the membrane internal to the cavity from sticking to the opposite side, which delimits the cavity downwardly.

Abstract: A multiphase DC-DC converter has two converter arrangements, each with a switching stage that has a switching node, an inductor, a converter output node, a high-side switch, and a low-side switch. Current sensing circuits detect the instantaneous current flowing through either the high-side or low-side switches, and signal time-averaging circuits produce time-averaged signals indicating the average current during a switch conduction interval. The time-averaged signals are added up and re-scaled based on the time period of the switching nodes' electrical coupling to the converter output nodes to generate an output signal for the average output current.

Abstract: A method of configuring a contactless communication device is provided. The contactless communication device includes integrated circuits hosting at least two applications compatible with different communication protocols or the same communication protocol and using different communication parameters and a contactless communication circuit. The method includes stopping, by the contactless communication circuit, the transmission of answers of the contactless communication device to requests transmitted by a proximity coupling reader during a transaction initiated by the reader to cause the initiation by the reader of a new transaction.

Abstract: A method and apparatus for performing dynamic current scaling of an input current of a voltage regulator are provided. The method and apparatus allow tuning current consumption in various applications, calculating a duration of an activity phase in which various algorithms are executed and activating dynamic current scaling of a regulator if the activity duration is shorter than a programmable threshold. A controller receives a threshold for an activity duration and a window size in which to evaluate the activity duration.

Abstract: A voltage regulator receives an input voltage and produces a regulated output voltage. A first feedback network compares a feedback signal to a reference signal to assert/de-assert a first pulsed control signal when the reference signal is higher/lower than the feedback signal. A second feedback network compares the output voltage to a threshold signal to assert/de-assert a second control signal when the threshold signal is higher/lower than the output voltage. A charge pump is enabled if the second control signal is de-asserted and is clocked by the first pulsed control signal to produce a supply voltage higher than the input voltage. A first pass element is enabled when the second control signal is asserted and is selectively activated when the first pulsed control signal is asserted. A second pass element is selectively activated when the second control signal is de-asserted.

Abstract: An infinite impulse response filter includes a plurality of lower order filter stages and a random number generator circuit. The plurality of lower order filter stages include a first filter stage coupled to a second filter stage. The random number generator circuit includes a first output coupled to the first filter stage and a second output coupled to the second filter stage. The random number generator circuit is configured to generate the same random value at both the first output and the second output. The infinite impulse response filter is an nth-order filter. The respective order of each of the lower order filter stages is less than n.

Abstract: A device including a transistor is fabricated by forming a first part of a first region of the transistor through the implantation of dopants through a first opening. The second region of the transistor is then formed in the first opening by epitaxy.

Abstract: A method for enhancing an image and an image enhancement device are described. The method for enhancing an image including: capturing an initial image including a plurality of pixels, and performing a pixel-by-pixel dehazing operation for each of the plurality of pixels. The performing including: generating, for each of the plurality of pixels, a value for a blended gray image based on color channels of the pixel, generating, for each of the plurality of pixels, a value for a transmission map based on the blended gray image, and generating, for each of the plurality of pixels, output color channels for a processed image based on the value for the transmission map, the processed image being an enhancement of the initial image.

Abstract: A physically unclonable function device includes a set of diode-connected MOS transistors having a random distribution of respective threshold voltages. A first circuit is configured to impose, on each first transistor, a fixed respective gate voltage regardless of the value of a current flowing in this first transistor. A second circuit is configured to impose, on each second transistor, a fixed respective gate voltage regardless of the value of a current flowing in this second transistor. A current mirror stage is coupled between the first circuit and the second circuit and is configured to deliver the reference current from a sum of the currents flowing in the first transistors. A comparator is configured to deliver a signal whose level depends on a comparison between a first current obtained from a reference current based on the first transistors and a second current of the second transistors.

Abstract: A digital audio playback circuit includes a noise shaping circuit configured to receive an input digital audio signal, and a digital to analog converter (DAC) configured to convert the input digital audio signal to a pre-amplified output analog audio signal according to a gain ramp defined by a gain control signal. A muting circuit is configured to compare input digital audio signal to a threshold and assert a mute control signal when the input digital audio signal is below the threshold. An analog gain control ramp circuit is configured to generate the gain control signal in response to the mute control signal to cause the gain ramp to ramp down. An amplifier is configured to amplify the pre-amplified output analog audio signal for playback by an audio playback device.

Abstract: A light-emitting diode has an anode terminal coupled to a node of application of a power supply voltage by a first transistor and a cathode terminal coupled to a node of application of a reference voltage by a second transistor. A microcontroller includes a digital-to-analog converter and a comparator, with the comparator having a first input coupled to one of the anode and cathode terminals of the diode and a second input configured to receive an output voltage of the converter. An output signal of the comparator controls one of the first and second transistors to turn off when the comparator detects an operating condition where current flow in the light-emitting diode exceeds maximum current limit (such as with the light-emitting diode operating in an exponential operating area.