Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity and a semiconductor layer disposed on the substrate and also having the first conductivity. A recess is disposed in the layer and has a sidewall and a bottom. A gate insulator is disposed on the layer and extends to the sidewall of the recess, and a gate is disposed on the gate insulator. A body region is disposed in the semiconductor layer beneath the gate, has a second conductivity, and is contiguous with the sidewall of the recess. A source region is disposed in the body region, has the first conductivity, and is contiguous with the sidewall. A Schottky contact is disposed on the bottom of the recess, and a source metallization is disposed on the Schottky contact and on the sidewall of the recess.

Abstract: For instruction clusters for which no significant performance penalty is incurred, such as execution of hardware loops, a processor automatically and dynamically switches to a pipelined two-cycle access to an associated associative cache rather than a single-cycle access. An access involving more than one cycle uses less power because only the hit way within the cache memory is accessed rather than all ways within the indexed cache line. To maintain performance, the single-cycle cache access is utilized in all remaining instructions. In addition, where instruction clusters within a hardware loop fit entirely within a pre-fetch buffer, the cache sub-system is idled for any remaining iterations of the hardware loop to further reduce power consumption.

Abstract: An electronic timer may include a clock reference signal generator and a real time clock (RTC) circuit for generating real time data based upon the clock reference signal. The RTC circuit may include a plurality of registers each for storing a respective bit of the real time data. Further, each register may include a master latch for initially storing the real time data bit, a slave latch for subsequently storing the real time data bit, and a user latch for storing the real time data bit from the slave latch. The RTC circuit may further include a controller for causing at least some of the registers to increment based upon the clock reference signal. Additionally, the electronic timer may also advantageously include a tamper circuit for receiving a tamper event signal and causing each of the user latches to hold a time stamp therein.

Abstract: A data sorting apparatus comprising 1) a storage sorter that sorts a data set according to a defined criteria; and 2) a query mechanism that receives intermediate sorted data values from the storage sorter and compares the intermediate sorted data values to at least one key value. The storage sorter comprises a priority queue for sorting the data set, wherein the priority queue comprises M processing elements. The query mechanism receives the intermediate sorted data values from the M processing elements. The query mechanism comprises a plurality of comparison circuits, each of the comparison circuits capable of detecting if one of the intermediate sorted data values is equal to the at least one key value or, if no match exists, extracting the minimal value greater than (or less than according to a defined criteria) the at least one key value.

Abstract: A method, apparatus and network device for controlling the flow of network data arranged in frames and minimizing congestion, such as in the receive port of an HDLC controller is disclosed. A status error indicator is generated within a receive FIFO memory indicative of a frame overflow within the receive FIFO memory. In response to the status error indicator, an early congestion interrupt is generated to a host processor indicative that a frame overflow has occurred within the receive FIFO memory. The incoming frame is discarded and the services of received frames are enhanced by one of either increasing the number of words of a direct memory access (DMA) unit burst size, or modifying the time-slice of other active processes.

Abstract: A method for estimating the motion between a first image and a second image in a system for creating a panoramic image from a plurality of images taken by a camera, the method comprising the steps of: downsampling a first image in a first direction and in a second direction; downsampling a second image in a first direction and in a second direction; filtering the first and the second image so as to filter out any global illumination changes between the first image and the second image; calculating a first displacement along the first direction between the first downsampled image along the first direction and the second downsampled image along the first direction; and calculating a second displacement along the second direction between the first downsampled image along the second direction and the second downsampled image along the second direction. In an alternate embodiment, a device and computer readable medium corresponding to the above method is described.

Abstract: A circuit is disclosed for monitoring a reference voltage generated in a semiconductor memory device to facilitate a memory access operation. The circuit utilizes a pair of Schmitt trigger circuits. A first of the Schmitt trigger circuits detects the voltage appearing on the output of a reference voltage generator falling below a minimum threshold voltage level. A second of the Schmitt trigger circuits detects the output voltage of the reference voltage generator exceeding a maximum threshold voltage level. The circuit may further include reset circuitry for initially placing predetermined voltage levels on the inputs of the Schmitt trigger circuits. An output circuit receives the output of each Schmitt trigger circuit and generates an output signal having a value indicative of whether the output of the reference voltage generator is not within an acceptable voltage range.

Abstract: A test mode structure and method of a multi-power-source device provides for the device to remain in a test mode, during which current draw of the device may be accurately measured, even after primary power supply to the device has been greatly reduced or completely removed. Significant reduction or removal of the primary power supply while still remaining in the test mode is necessary to counter the presence of a variable current that would otherwise be normally generated by the multi-power-source device in the test mode; the presence of the variable current during the test mode, if not negated, will not permit an accurate measurement of the current draw of the multi-power-source device. Significant reduction or removal of the primary power supply to the device would typically cause the multi-power-source device to exit the test mode and switch to a secondary supply voltage supplied by the secondary power supply, thereby foiling any attempt to measure the current draw of the device.

Abstract: A clock control circuit for use in a multi-channel baud-rate timing recovery loop includes a control circuit responsive to a phase error signal from at least one phase detector for generating at least one clock control signal, wherein said control circuit propagates adjustments required for frequency correction in a synchronous fashion across all of the N-channels.

Abstract: A method and network device are disclosed using a look-ahead watermark in a FIFO memory. In accordance with the present invention, a watermark interrupt is generated from a FIFO memory when data in the FIFO memory has crossed a watermark threshold. A data burst is transferred through a direct memory access unit to the FIFO memory. A look-ahead watermark flag is checked at the FIFO memory to determine if sufficient memory space exists inside the FIFO memory for an additional data burst, which is transferred through the direct memory access unit to the FIFO memory when the look-ahead watermark flag indicates that sufficient memory space is available.

Abstract: A touch-sensitive semiconductor chip having a physical interface to the environment, where the surface of the physical interface is coated with a fluorocarbon polymer. The polymer is highly scratch resistant and has a characteristic low dielectric constant for providing a low attenuation to electric fields. The polymer can be used instead of conventional passivation layers, thereby allowing a thin, low dielectric constant layer between the object touching the physical interface, and the capacitive sensing circuits underlying the polymer.

Abstract: Disclosed is a peripheral device for reliably detecting synchronization patterns in CD-ROM media. The peripheral device has an internal circuitry for controlling and processing data that is read from a medium of the peripheral device is disclosed. The peripheral device comprises a digital signal processor, a decoder circuit, and a state machine. The digital signal processor is configured to receive the data that is being read from the medium of the peripheral device. The decoder circuit is coupled to the digital signal processor and forms a part of the internal circuitry. Further, the decoder circuit includes an internal RAM that is configured to store a sector of the data including a current sync pattern and a next sync pattern. The state machine resides in the decoder for analyzing the current sync pattern and the next sync pattern of the sector of the data. In the analysis mode, the state code is configured to determine whether a fatal error is present in the data.

Abstract: Reference generator circuitry for providing a reference to sense amplifiers in a flash memory device. The circuitry includes a reference current generator for generating a reference current for use by the sense amplifier circuits. A current buffer circuit in the flash memory device mirrors the reference current and applies a plurality of mirrored reference currents to the reference inputs of the sense amplifiers. A startup circuit is utilized in order to provide a fast settling time of the reference node appearing at the input of the sense amplifiers. The startup circuit includes first and second discharge current stages, with the first discharge current stage discharging the charge appearing at the reference node input of the sense amplifiers based upon a bandgap reference current. The second discharge current stage discharging the charge appearing at the reference node input of the sense amplifiers based upon the reference current.

Abstract: A preformed adhesive layer for joining components within integrated circuit packaging includes venting slots for controlling the size and location of voids within an assembled integrated circuit package. Air randomly entrapped between the surfaces of the adhesive layer and adjoining components during assembly will generally release into the venting slots during subsequent assembly and/or mounting steps performed at elevated temperatures, rather than creating internal pressures causing separation of package components or releasing into the encapsulant. Die delamination and encapsulant void problems occurring during reflow or other assembly and mounting processes as a result of entrapped air are avoided.

Abstract: An integrated circuit includes a sensor that reads a fingerprint and provides data corresponding to the fingerprint to a computation engine coupled to the sensor. The computation engine compares the data to stored data and enables a smart card coupled to the computation engine when the data and the stored data match. The computation engine may include an array of flash memory cells arranged in pairs of rows, where flash memory cells in any one row have sources coupled to a common row line and a plurality of conductance mode neurons each having first and second inputs coupled to first and second row lines forming a respective pair of rows. The neurons are coupled to the flash memory cells through a buffer circuit sets a drain-source voltage of the flash memory cells in the row pair coupled to the neuron.

Abstract: A semiconductor structure includes a substrate, a dielectric layer disposed on the substrate, a layer of undoped silicate glass disposed on the dielectric layer, a layer of borophosphorous silicate glass on the layer of undoped silicate glass, and a planar dielectric layer disposed on the layer of borophosphorous silicate glass, the layers of undoped silicate glass, borophosphorous silicate glass, and planar dielectric together forming a pre-metal dielectric stack. The planar dielectric may include plasma-enhanced tetraethyl orthosilicate.

Abstract: An integrated circuit (IC) device comprising: 1) an integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and sidewalls extending between the first surface and the second surface; and 2) an integrated circuit (IC) package for supporting the IC die, wherein the IC package is attached to at least one of the sidewalls of the IC die such that at least a portion of the IC die first surface and at least a portion of the IC die second surface are exposed.

Abstract: A method and circuit are disclosed for measuring temperature. An exemplary embodiment of the present invention includes a first oscillator circuit that generates a first signal having a frequency that is dependent upon a sensed temperature. Difference circuitry determines a difference in frequency between the first signal and the second signal having a frequency that is substantially independent of temperature, and generates a difference signal having a number of pulses thereon based upon the difference. A counter circuit is responsive to the difference circuitry for offsetting a predetermined temperature level based upon the pulses appearing on the difference signal, to obtain an output signal indicative of the sensed temperature.

Abstract: A method and device are disclosed for detecting successful transfers between a Universal Serial Bus (USB) port and a USB smart card and generating a signal that provides an indication of the USB transaction activity. This USB transaction activity signal is modulated according to the USB transaction activity and drives a Light Emitting Diode (LED) in a preferred embodiment of the invention. A counter internal to the USB smart card scales the transaction activity signal such that it is perceptible to the user. Because the current through the LED depends upon the USB transaction activity, the brightness of the LED varies according to the USB transaction activity. The LED may be driven from a current mirror sink or source, or a current switch sink or source.

Abstract: A multi-mode motor controller architecture includes a motor, an integrated circuit controller, and an integrated circuit driver circuit. The integrated circuit controller includes a pulse generator, a DAC, an ADC, and a digital compensator circuit. The integrated circuit driver circuit is in communication with the controller and includes an error amplifier, first and second output amplifiers for driving the motor, and a sense amplifier. The motor controller architecture is configurable to operate in a linear mode, a pulsed mode, or a switchable linear/pulsed mode. The controller architecture can be implemented with external compensation circuitry, such as a resistor-capacitor circuit, or with the digital compensation circuitry located within the controller integrated circuit.