Abstract: A battery pack for two 2032 batteries includes a molded plastic base having an upper surface on which the batteries are received and columnar standoff posts projecting from a bottom surface, as well as a molded plastic housing sized to receive the batteries and an upper portion of the base and having ears through which screws are passed to be received by press-fit threaded inserts mounted on an integrated circuit packaging substrate and tightened to a predetermined torque. Like terminals of the batteries are joined by a welded plate, with conductive pins connected to each plate extending through the base and projecting from a bottom surface of the battery pack. A mounting guide ensures connection of proper pins to corresponding receptacles during mounting of the battery pack on the integrated circuit packaging substrate.

Abstract: An image processing system and method reconstructs 3D image information corresponding to a scene from a plurality of 2D images of the scene. The method receives a plurality of image features corresponded between different 2D views of the scene, the corresponded image features deviating between different views as a result of camera relative motion. The method determines image features of the received plurality of image features that are occluded views, determines image features of the received plurality of image features that are confident seeds associated with 3D depth information, and propagates 3D depth information from the confident seeds to neighboring image features, while avoiding image features that have been determined to be occluded views. The 3D image information can be rendered and displayed such as for a virtual walkthrough of the scene.

Abstract: A substrate clamp ring has an edge exclusion lip with a variable bottom surface. At least a portion of that bottom surface has a height above the substrate contact level selected to minimize accumulation over time of deposited aluminum-copper alloy across lower portions of the bottom surface, and to allow the aluminum-copper alloy to be deposited to a thickness of at least 2 microns on each of a predetermined number of substrates without bridging. The height of the bottom surface at an innermost edge of the lip is preferably about 17 mils, while a height of the bottom surface over the substrate edge is preferably about 8.5 mils.

Abstract: An image processing system and method for smoothing irregularities from 3D image information that was reconstructed from a plurality of 2D views of a scene, and particularly from homogeneous surfaces of objects in a scene. The method defines a window that overlaps a plurality of pixels of one of a plurality of 2D image views of a scene. Each pixel is associated with predefined 3D depth information, and further is associated with a matching curve. A subject pixel is located within the plurality of pixels overlapped by the window. The method calculates an average 3D depth information associated with the plurality of pixels overlapped by the window, and assigns the calculated average 3D depth information to the 3D depth information of the subject pixel, if the calculated average 3D depth information is within an error region of a matching curve associated with the subject pixel.

Abstract: An electrically floating capacitor plate defines a sensing capacitor with a fingerprint sensing surface thereabove. A reference voltage pulse is selectively applied to a pixel input node that is capacitively coupled to the floating plate, which in turn is capacitively coupled to the input node of a charge integrator. During a sensing operation, the charge integrator generates a pixel output signal that is a function of the variable capacitance of the sensing capacitor, which corresponds to a ridge or valley fingerprint characteristic that appears directly above the floating plate.

Abstract: A flat filter layer is received between upper and lower mold portions of a mold for packaging an integrated circuit sensor device, held by the mold over and in contact with the integrated circuit's sensing surface, in light compression between the sensing surface and a mold surface. The filter layer includes slots allowing passage of injected encapsulating material to cover the integrated circuit die, with overlap portions embedded in the encapsulating material, while preventing such encapsulating material from flowing onto the sensing surface. The filter layer may be, for example, a liquid and/or light filter, and may include a protective or supportive backing. The filter is thus affixed to the packaged integrated circuit sensor device, while mold residue is reduced and mold life extended.

Abstract: An electronic circuit includes a selectively configurable differential signal interface and a selection control input for selecting one of a plurality of standard differential signal interfaces for configuration of the differential signal interface. The selection control input selects one of the following plurality of standard differential signal interfaces: reduced swing differential signaling (RSDS), low voltage differential signaling (LVDS), mini low voltage differential signaling (mini-LVDS), and bussed low voltage differential signaling (BLVDS), for configuration of the differential signal interface. The electronic circuit may also include a plurality of selectable voltage sources (611, 612, 613) and a plurality of selectable current sources (614, 615, 616, 617), for selecting, in response to an input signal at the selection control input, at least one of an operating D.C. voltage, a standard differential signal voltage, and a standard differential signal current for the differential signal interface.

Abstract: A system and method of advancing the commutation sequence of a brushless DC motor is provided. The motor having a plurality of coils, each of the coils coupled together at one end to a common center tap and coupled at an opposite end, through a respective coil tap, to both a source voltage and ground via selectively actuateable switches having diodes coupled in parallel therewith. The motor operates in a pulse width modulation (PWM) mode having PWM-on states and PWM-off states. During PWM-off states, a coil tap voltage from the coil tap of a floating phase is provided to a preconditioning circuit. The preconditioning circuit adjusts the floating phase coil tap voltage to compensate for an amount of voltage substantially equal to an amount of voltage by which a voltage at the center tap deviates from zero. The preconditioning circuit further includes sharpening circuitry for amplifying the adjusted floating phase coil tap voltage.

Abstract: A component of an image processor receives at least a portion of one or more reconstructed versions of an image including a causal context of an object pixel of the image, and provides a prediction for the object pixel computed as a weighted sum according to at least one measure of correlation and a weighting policy. A component receives a first prediction of an object pixel and reconstructed versions of an image, and provides a second prediction for the object pixel in accordance with the first prediction for the object pixel and a substantially mean error for the context. A component receives one or more prediction differences versions of the image including a causal context prediction difference of an object prediction difference of the image, and provides a prediction for the object prediction difference computed as a weighted sum according to at least one measure of correlation and a weighting policy.

Abstract: Enhanced resolution video sequence results from construction of enhanced resolution key frames and synthesis of enhanced resolution non-key frames. Key frames are constructed by processing a plurality of initial resolution frames in order to produce the enhanced resolution image components of the key frame. Non-key frames are synthesized using the enhanced resolution image component of the key frames and image component motion determinations from initial resolution frames using an image warping technique. Non-key frame image components are further improved by blending and error correction processes.

Abstract: A method and apparatus to control application of a drive current to a voice coil in a hard disk drive system modulates a periodic waveform between either a reference level and a signal associated with a stored back electromotive force (BEMF) in the voice coil. The drive current is applied to the voice coil during periods of time when the periodic waveform is modulated by the signal associated with the stored BEMF. The amplitude and duration of the drive current correspondingly decreases as the BEMF in the voice coil decreases. Thus, the voice coil is controlled based on its BEMF and is provided with decreasing power to move a head mechanism to or from a ramp assembly.

Abstract: A system includes an integrated circuit device that compares the relative phase of first and second signals to a very high precision. The system includes a first input for receiving the first signal with a first edge, and a second input for receiving the second signal with a second edge. A first delay chain includes a first at least one delay element, and the first signal is delayed across the first at least one delay element, each of the first at least one delay element includes an output tap. A second delay chain includes a second at least one delay element, the second signal is delayed across the second at least one delay element, each of the second at least one delay element includes an output tap.

Abstract: A narrow array optical fingerprint detector that substantially eliminates over-sampling of the array measures the speed of a finger moving over the array and scans the array at a rate determined by the speed of movement of the finger. The fingerprint detector measures the speed of finger movement with a transparent cylinder rotatably mounted adjacent the array. The transparent cylinder is mounted to engage the finger and rotate as the finger is swept past the array. A light chopper is mounted for rotation with the cylinder. A photo-sensor is mounted adjacent the light chopper. The photo-sensor produces a signal in response to light being chopped by the light chopper. The photo-sensor is operably connected to scanning circuitry. Each time the scanning circuitry receives a signal from the photo-sensor, the scanning circuitry scans the array.

Abstract: An iterative method and system are disclosed for locating errors in interleaved code words. The system and method generate column parity check symbols using symbols from selected columns in the interleaved code words. The width of each column parity check symbol is reduced, followed by the reduced column parity check symbols being merged to create merged column check symbols. A Reed-Solomon encoding algorithm is performed on the merged column check symbols to generate error locating check symbols which are combined with the reduced column parity check symbols to create an error locating code word. The error locating check symbols are stored with the interleaved code words in memory. Following retrieval from memory, the error locating code word is reconstructed and decoded upon the detection of at least one uncorrectable interleaved code word from decoding the interleaved code words.

Abstract: There is disclosed a field programmable gate array (FPGA) that performs bit swapping functions in the interconnects rather than in the configurable logic blocks of the FPGA.

Abstract: A communication system includes a receiver for receiving a serial bit stream from at least one communication channel, and a decoder, in communication with the receiver, for decoding words from the received serial bit stream, the words being defined at least in part by word boundaries in the received serial bit stream. The decoder contemporaneously synchronizes detection of bits and detection of the word boundaries in the received serial bit stream. The decoder preferably decodes digitized video signal information in the serial bit stream according to a Transition Minimized Differential Signalling protocol. The receiver and decoder are preferably part of an integrated circuit chip.

Abstract: A system and method is disclosed for providing a redistribution metal layer in an integrated circuit. The redistribution metal layer is formed from the last metal layer in the integrated circuit during manufacture of the integrated circuit before final passivation is applied. The last metal layer provides sites for solder bump pads used in flip chip interconnection. The redistribution metal layer can be (1) a flat layer deposited over the next to last metal layer through an opening in a dielectric layer, or (2) deposited over an array of vias connected to the next to last metal layer. Space between the solder bump pads is deposited with narrower traces for connecting active circuit areas below. A final passivation layer is deposited to ensure product reliability.

Abstract: Disclosed is a fault tolerant CMOS image sensor that includes circuitry for identifying defective pixels and masking them during image generation. Masking may involve, in one example, replacing the output of a given pixel with an average of the output of surrounding non-faulty pixels. Thus, while image sensors may be fabricated with some number of faulty pixels, the images produced by such sensors will not have undesirable bright or dark spots. The disclosed sensor includes (a) one or more pixels (active or passive) capable of providing outputs indicative of a quantity of radiation to which each of the one or more pixels has been exposed; and (b) one or more circuit elements electrically coupled to the one or more pixels and configured to identify and correct faulty pixels in the CMOS imager. The one more pixels each include a photodiode diffusion formed in a well and a tap to power or ground also formed in the well.

Abstract: A system and method is provided for placing gate capacitors, or other performance enhancing electrical components, in an under-utilized standard cell region. The present invention is a layout design tool that allows the designed to automatically intersperse capacitor filler cells around standard cell logic. The present invention includes creating a region, allocated to the particular standard cell, which has (either by intention or situation) low utilization. The design tool of the present invention can also be used to intentionally under-utilize various functional blocks in order to create areas that can be filled with cells containing gate capacitors. The standard cells may or may not be associated with surrounding logic. The place and route filler cells are redefined to include gate capacitors using abutment rules compatible with the standard cells.

Abstract: According to the present invention, a circuit, utilizing a minimum number of bipolar devices and current mirror scaling devices, generates a bandgap reference voltage. The bandgap voltage generated by the bandgap reference circuit is a function of a plurality of sized current mirror devices, the ratio of a first resistor to a second resistor, and the number and relative sizing of bipolar junction transistors used. The bandgap reference circuit generates a bandgap reference voltage which is suitable for use in a variety of integrated circuit devices, such as a zero power static random access memory (SRAM). If used in a zero power SRAM application, the bandgap reference voltage may be utilized to determine when the primary power source of the zero power SRAM has fallen below a predetermined voltage level and a secondary power source must be substituted for the primary power source.