Patents Assigned to STMicroelectronics, Inc.
  • Publication number: 20020070452
    Abstract: This invention relates to a method for manufacturing a semiconductor device having polysilicon lines with micro-roughness on the surface. The micro-rough surface of the polysilicon lines help produce smaller grain size silicide film during the formation phase to reduce the sheet resistance. The micro-rough surface of the polysilicon lines also increases the effective surface area of the silicide contacting polysilicon lines thereby reduces the overall resistance of the final gate structure after metallization.
    Type: Application
    Filed: February 6, 2002
    Publication date: June 13, 2002
    Applicant: STMicroelectronics Inc.
    Inventor: Ming Michael Li
  • Patent number: 6403427
    Abstract: A field-effect transistor and a method for its fabrication are described. The transistor includes a monocrystalline channel region extending from a monocrystalline body region of a semiconductor substrate. First and second source/drain regions laterally adjoin opposite sides of the channel region and are electrically isolated from the body region by an underlying first dielectric layer. The source/drain regions include both polycrystalline and monocrystalline semiconductor regions. A conductive gate electrode is formed over a second dielectric layer overlying the channel region. The transistor is formed by selectively oxidizing portions of a monocrystalline semiconductor substrate and then removing portions of the oxidized substrate. The resulting structure includes a body region of the substrate having overlying first and second oxide regions, with a protruding channel region extending from the body region between the oxide regions.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: June 11, 2002
    Assignee: STMicroelectronics, Inc.
    Inventor: Richard A. Blanchard
  • Publication number: 20020067301
    Abstract: An analog-to-digital converter (500) for sampling high speed video signals includes a first input (502) for receiving an electronic signal, a sampling clock input (547) for receiving a sampling clock signal, and first and second sampling circuits. The first sampling circuit is arranged in a differential circuit arrangement, and is electrically connected to the first input (502) and to the sampling clock input (547) and is responsive to the sampling clock signal, for sampling the electronic signal to provide a pair of boundary reference voltage signals (706, 708, 710, 712) that bound the voltage of the sampled electronic signal, and further to convert the sampled electronic signal to provide the most significant bits (554) of a digital representation of the electronic signal at times indicated by the sampling clock signal.
    Type: Application
    Filed: December 1, 2000
    Publication date: June 6, 2002
    Applicant: STMicroelectronics, Inc.
    Inventor: Gunter W. Steinbach
  • Patent number: 6399961
    Abstract: A field-effect transistor and a method for its fabrication are described. The transistor includes a monocrystalline channel region extending from a monocrystalline body region of a semiconductor substrate. First and second source/drain regions laterally adjoin opposite sides of the channel region and are electrically isolated from the body region by an underlying first dielectric layer. The source/drain regions include both polycrystalline and monocrystalline semiconductor regions. A conductive gate electrode is formed over a second dielectric layer overlying the channel region. The transistor is formed by selectively oxidizing portions of a monocrystalline semiconductor substrate and then removing portions of the oxidized substrate. The resulting structure includes a body region of the substrate having overlying first and second oxide regions, with a protruding channel region extending from the body region between the oxide regions.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: June 4, 2002
    Assignee: STMicroelectronics, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 6395629
    Abstract: An improved method for fabricating interconnect signal lines in integrated circuits utilizes variations from standard process conditions to relieve stress during formation of metal signal lines. This prevents AlCu stress migration and TiN ARC cracking caused by subsequent high temperature processing. A relatively planar interconnect layer, being one which does not extend through an insulating layer to make contact with an underlying conductor, includes an initial wetting layer of Ti formed over a Ti/TiN layer remaining from earlier processing steps. An AlCu layer is deposited over the Ti at a high temperature with a low deposition rate. Finally, a TiN ARC layer is formed in the usual manner. However, decreased nitrogen flow during deposition lowers the nitrogen content of the ARC layer and prevents later cracking. Deposition conditions for the AlCu layer prevent the formation of voids during subsequent high temperature processing steps.
    Type: Grant
    Filed: April 16, 1997
    Date of Patent: May 28, 2002
    Assignee: STMicroelectronics, Inc.
    Inventors: Ardeshir J. Sidhwa, Stephen John Melosky
  • Patent number: 6392577
    Abstract: A system and method regulates an alternator and includes a circuit for digitally generating a sawtooth waveform. An error amplifier circuit generates a divided down and error amplified alternator system voltage. A comparator circuit receives and compares to each other the digitally generated sawtooth waveform and the error amplified alternator system voltage and has an output to produce an alternator field input signal used for driving the field of an alternator.
    Type: Grant
    Filed: October 5, 1999
    Date of Patent: May 21, 2002
    Assignees: STMicroelectronics, Inc., STMicroelectronics S.r.l.
    Inventors: David F. Swanson, Mauro Merlo, Franco Cocetta
  • Patent number: 6392636
    Abstract: A plurality N of capacitance sensing cells are arranged in a row/column array top to cooperate with a fingertip and produce an output signal that controls the movement of a cursor/pointer across a display screen. The output of each individual sensing cell is connected to the corresponding individual node of a resistor array that has N nodes arranged in a similar row/column array. A centroid output of the resistor nodes in row configuration provides an output signal for control of cursor movement in a row direction. A centroid output of the resistor nodes in column configuration provides an output signal for control of cursor movement in an orthogonal column direction. A mass signal output of the row/column resistor mode array provides a switch on/off signal.
    Type: Grant
    Filed: January 22, 1998
    Date of Patent: May 21, 2002
    Assignee: STMicroelectronics, Inc.
    Inventors: Alberto Ferrari, Marco Tartagni
  • Publication number: 20020053951
    Abstract: An integrated circuit chip includes an RC oscillator circuit. The frequency of the output signal generated by the oscillator output signal is set as a function of a value of an included internal resistor integrated on the chip. An external resistor may be connected to the chip to allow a user to manipulate the oscillator output signal frequency. A detection circuit on the chip detects the presence of the connected external resistor. Responsive to that detection, a substitution circuit operates to substitute the connected external resistor for the internal resistor in the RC oscillator circuit. This effectuates a change of the frequency of the oscillator output signal to instead be set as a function of a value of that connected external resistor.
    Type: Application
    Filed: December 27, 2001
    Publication date: May 9, 2002
    Applicant: STMicroelectronics, Inc.
    Inventor: Lijun Tian
  • Patent number: 6383905
    Abstract: This invention relates to a method for manufacturing a semiconductor device having polysilicon lines with micro-roughness on the surface. The micro-rough surface of the polysilicon lines help produce smaller grain size silicide graiicide film during the formation phase to reduce the sheet resistance. The micro-rough surface of the polysilicon lines also increases the effective surface area of the silicide contacting polysilicon lines thereby reduces the overall resistance of the final gate structure after metallization.
    Type: Grant
    Filed: July 31, 1998
    Date of Patent: May 7, 2002
    Assignee: STMicroelectronics, Inc.
    Inventor: MingT Michael Lee
  • Patent number: 6381115
    Abstract: A redundant electric fuse circuit is provided that includes a plurality of fuses coupled in series and each having a fuse control device operable for generating a current through each fuse sufficient to blow the fuse. A first fuse control signal is activated to generate a sufficient current through one of the fuses to blow the fuse. A second fuse control signal is activated to generate a sufficient current through the other fuse to blow that fuse. The electric fuse circuit provides redundancy thereby increasing the yield of integrated circuits by reducing the probability that a defective fuse (i.e., a fuse that reforms after blowing) will cause a fatal defect in the integrated circuit.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: April 30, 2002
    Assignee: STMicroelectronics, Inc.
    Inventors: Tsiu Chiu Chan, Elmer Henry Guritz
  • Patent number: 6380598
    Abstract: A radiation hardened memory device having static random access memory cells includes active gate isolation structures to prevent leakage currents between active regions formed adjacent to each other on a substrate. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a voltage terminal resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: April 30, 2002
    Assignee: STMicroelectronics, Inc.
    Inventor: Tsiu C. Chan
  • Patent number: 6373650
    Abstract: A voice coil motor control circuit provides control signals to a voice coil motor circuit drivel that is coupled to a voice coil motor. A current sensing resistor is coupled in series with the voice coil motor. The control circuit includes a sense amplifier having inputs that couple to the current sensing resistor and includes a feedback circuit that includes an input and also includes an output that couples to the voice coil motor driver. In a first mode of operation, the feedback circuit input is coupled to an output of the sense amplifier. The control circuit also includes an inverting operational amplifier. In the first mode of operation, the inverting operational amplifier is bypassed. In a second mode of operation corresponding to deployment of a read/write head from a parked position onto the disc, the inverting operational amplifier is coupled in series between the sense amplifier output and the feedback circuit input.
    Type: Grant
    Filed: August 20, 1998
    Date of Patent: April 16, 2002
    Assignee: STMicroelectronics, Inc.
    Inventor: Giorgio Pedrazzini
  • Patent number: 6373737
    Abstract: A content addressable memory includes a memory array having a plurality of entries. Control circuitry is provided for sequentially presenting each entry in the array to a comparator. An input signal is also provided to the comparator. Entries matching the input signal are identified for later use. The input signal can be masked, so that only selected fields of each entry are compared to it. Conventional RAM technology can be used for the memory array. In the alternative, a serial memory array, such as an array formed from a charge coupled device, can be used.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 16, 2002
    Assignee: STMicroelectronics, Inc.
    Inventor: Mark A. Lysinger
  • Patent number: 6372543
    Abstract: An apparatus and method for producing a wrap-around interconnect substrate (60) comprising a substrate (42) having semi-circular vias (62) having openings (64) created by separating through cylindrical vias (62) that were positioned along cutting lines (46a, 46b) that formed part of an integrated circuit substrate strip (40) prior to separation, is disclosed.
    Type: Grant
    Filed: May 8, 2000
    Date of Patent: April 16, 2002
    Assignee: STMicroelectronics, Inc.
    Inventors: Anthony Chiu, Tom Quoc Lao, Harry Michael Siegel, Michael J. Hundt
  • Patent number: 6370115
    Abstract: An Ethernet device and the method for applying back pressure within an Ethernet communication network comprising the steps of asserting a back pressure pin of a media access control unit associated with a network communications port of an Ethernet device. In response to asserting the back pressure pin, only the back pressure continuous preamble of a packet is transmitted without a start-of-frame delimiter onto the network.
    Type: Grant
    Filed: September 9, 1998
    Date of Patent: April 9, 2002
    Assignee: STMicroelectronics, Inc.
    Inventor: Alexander A. Smith
  • Patent number: 6369534
    Abstract: A circuit and method are disclosed for determining whether a brushless polyphase motor is spinning in a reverse direction relative to spin direction during normal operation. The circuit receives a back emf signal of a first phase line and determines a polarity of the back emf signal following a back emf signal associated with a second phase line crossing a zero reference level. Based upon the determined polarity of the back emf signal of the first phase line, the circuit selectively asserts an output signal indicating that the motor is spinning in the reverse direction.
    Type: Grant
    Filed: April 26, 2000
    Date of Patent: April 9, 2002
    Assignee: STMicroelectronics, Inc.
    Inventor: Paolo Menegoli
  • Patent number: 6365496
    Abstract: A contact opening to a silicon substrate within which a metal contact is to be formed is cleaned by soft sputter etch to clean the substrate surface and remove any residue which would interfere with formation of a continuous silicide layer across the contact region. Contact profile protrusion at the interface between two dielectrics forming the insulating material through which the contact opening is formed is also reduced by the soft sputter etch. A barrier is formed over the contact region utilizing two discrete deposition steps, preferably separated by an interval of time and employing different process parameters, to provide a shift in the grain boundaries between the two barrier layers, creating diffusion traps at grain discontinuities inhibiting the diffusion of metal through the barrier layer. Performance of the barrier layer in preventing junction spiking is thereby increased.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: April 2, 2002
    Assignee: STMicroelectronics, Inc.
    Inventor: Ardeshir J. Sidhwa
  • Patent number: 6366225
    Abstract: A phase-calculation circuit includes a buffer, an approximation circuit, and an interpolator. The buffer receives and stores first and second samples of a periodic signal having a peak amplitude. The approximation circuit linearly approximates a portion of the periodic signal, and calculates the relative phase of one of the samples within the signal portion. The interpolator then calculates the absolute phase of the one sample with respect to a predetermined point of the signal using the relative phase of the sample within the signal portion and the values of the first and second samples. Such a circuit can be used to decrease the alignment-acquisition time of a digital timing-recovery loop, and thus allows a shortening of the preamble and a corresponding increase in the data-storage density of a disk. In one application, the circuit determines an initial phase difference between a disk-drive read signal and a read-signal sample clock.
    Type: Grant
    Filed: February 14, 2000
    Date of Patent: April 2, 2002
    Assignee: STMicroelectronics, Inc.
    Inventor: Hakan Ozdemir
  • Patent number: 6365991
    Abstract: A test mode structure and method of a multi-power-source device provides for the device to remain in a test mode, during which current draw of the device may be accurately measured, even after primary power supply to the device has been greatly reduced or completely removed. Significant reduction or removal of the primary power supply while still remaining in the test mode is necessary to counter the presence of a variable current that would otherwise be normally generated by the multi-power-source device in the test mode; the presence of the variable current during the test mode, if not negated, will not permit an accurate measurement of the current draw of the multi-power-source device. Significant reduction or removal of the primary power supply to the device would typically cause the multi-power-source device to exit the test mode and switch to a secondary supply voltage supplied by the secondary power supply, thereby foiling any attempt to measure the current draw of the device.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: April 2, 2002
    Assignee: STMicroelectronics, Inc.
    Inventors: Tom Youssef, David Charles McClure
  • Patent number: RE37708
    Abstract: A method for reducing the transient response time of a voltage regulator when the load attached to it is entering or exiting a lower power consumption level by changing the bandwidth of the voltage regulator without compromising its stability, and a bandwidth regulator for implementing such a method are disclosed, wherein the bandwidth of the voltage regulator is changed based on a signal sent by a control device when it senses that the component is about to change power consumption levels.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: May 21, 2002
    Assignee: STMicroelectronics, Inc.
    Inventor: Eric J. Danstrom