Abstract: A method and network device are disclosed using a look-ahead watermark in a FIFO memory. In accordance with the present invention, a watermark interrupt is generated from a FIFO memory when data in the FIFO memory has crossed a watermark threshold. A data burst is transferred through a direct memory access unit to the FIFO memory. A look-ahead watermark flag is checked at the FIFO memory to determine if sufficient memory space exists inside the FIFO memory for an additional data burst, which is transferred through the direct memory access unit to the FIFO memory when the look-ahead watermark flag indicates that sufficient memory space is available.

Abstract: A field-effect transistor and a method for its fabrication is described. The transistor includes a monocrystalline semiconductor channel region overlying and epitaxially continuous with a body region of a semiconductor substrate. First and second semiconductor source/drain regions laterally adjoin opposite sides of the channel region and are electrically isolated from the body region by an underlying first dielectric layer. The source/drain regions include both polycrystalline and monocrystalline semiconductor material. A conductive gate electrode is formed over a second dielectric layer overlying the channel region. The transistor is formed by patterning the first dielectric layer to selectively cover a portion of the substrate and leave an exposed portion of the substrate.

Abstract: The invention provides a method and system for performing instructions in a microprocessor having a set of registers, in which instructions which operate on portions of a register are recognized, and “stitching” instructions are inserted into the instruction stream to couple the instructions operating on the portions of the register. The “stitching” parcels are serialized along with other instruction parcels, so that instructions which read from or write to portions of a register can proceed independently and out of their original order, while maintaining the results of that out-or-order operation to be the same as if all instructions were performed in the original order. In a preferred embodiment, the choice of stitching parcels is optimized to the Intel x86 architecture and instruction set.

Abstract: A cantilevered beam is formed over a cavity to an accurate length by isotropically etching a fast-etching material, such as hydrogen silisquioxane, out of the cavity. The cavity is initially defined within a slow-etching material. The selectivity of the etch rates of the material within the cavity relative to the material defining the walls of the cavity permits accurate control of the length of the free end of the cantilevered beam. The resonant frequency of the cantilevered beam can be tuned to a narrow predetermined range by laser trimming.

Abstract: A ballast compatible with different types of gas discharge lamps includes a power supply and a controller connected to the power supply. The controller includes a memory having a plurality of desired operating parameters stored therein for respective different types of gas discharge lamps. A sensing circuit causes the power supply to supply a current to the gas discharge lamp prior to start-up and senses a voltage based thereon indicative of a type of the gas discharge lamp. A control circuit causes the power supply to provide the desired operating parameters based upon the type of gas discharge lamp. Since the desired operating parameters are applied to the gas discharge lamp, the life of the lamp is increased.

Abstract: An integrated circuit includes a sensor that reads a fingerprint and provides data corresponding to the fingerprint to a computation engine coupled to the sensor. The computation engine compares the data to stored data and enables a smart card coupled to the computation engine when the data and the stored data match. The computation engine may include an array of flash memory cells arranged in pairs of rows, where flash memory cells in any one row have sources coupled to a common row line and a plurality of conductance mode neurons each having first and second inputs coupled to first and second row lines forming a respective pair of rows. The neurons are coupled to the flash memory cells through a buffer circuit sets a drain-source voltage of the flash memory cells in the row pair coupled to the neuron.

Abstract: A structure and method is disclosed for dissipating electrostatic charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry, and a conductive layer and passivation layers disposed over the underlying dielectric layer wherein the conductive layer diffuses electrostatic charges at the surface of the integrated circuit.

Abstract: A dual-mode IC is provided for operating in first mode such as an ISO mode in accordance with International Standards Organization 7816 (ISO 7816) protocol, and a second, non-ISO mode, such as a USB mode in accordance with Universal Serial Bus (USB) protocol. The dual-mode IC is preferably in a smart card and includes a microprocessor, a switching block, and an external interface. The external interface includes a voltage supply pad, a reference voltage pad, a reset pad, a clock pad and an input/output pad in accordance with the ISO 7816 protocol, and a D-plus pad and D-minus pad in accordance with the USB protocol. The IC further includes a mode configuration circuit for detecting a USB mode condition on at least one of the D-plus and D-minus pads, and configuring the IC in the ISO mode or the USB mode depending on the result. Once the IC is configured in a particular mode, it will operate in only that mode until the next power-on reset sequence.

Abstract: A memory device having redundancy is disclosed. The memory device includes an array of memory cells organized into rows and columns of memory cells, each row of memory cells including a plurality of addressable memory cells and redundant memory cells, the array of memory cells including row lines and column lines, each row line being coupled to memory cells in a distinct row of memory cells, each column line being coupled to memory cells in a distinct column of memory cells, and column input/output lines. The memory device further includes a redundancy circuitry for selectively coupling column lines to column input/output lines of the array of memory cells and selectively decoupling at least one column line from the column input/output lines, based upon an address value received by the memory device during a memory access operation.

Abstract: A distance sensor has a capacitive element in turn having a first capacitor plate which is positioned facing a second capacitor plate whose distance is to be measured. In the case of fingerprinting, the second capacitor plate is defined directly by the skin surface of the finger being printed. The sensor comprises an inverting amplifier, between the input and output of which the capacitive element is connected to form a negative feedback branch. By supplying an electric charge step to the input of the inverting amplifier, a voltage step directly proportional to the distance being measured is obtained at the output.

Abstract: A heat sink is mounted on an integrated circuit die within a Chip Scale Package, without a substrate supporting the heat sink. The heat sink may be mounted on a central portion of the active surface of the integrated circuit die without impeding wire bond connection of bond pads around peripheral region of the active surface. Alternatively, the heat sink may be mounted on the backside of one integrated circuit die within a stacked configuration of integrated circuits having facing active surfaces. The required form factor for Chip Scale Packages is maintained while providing heat dissipation for high input/output devices. The heat sink may be wire bonded to a ground connection to provide the packaged integrated circuit with shielding from electrical or electromagnetic interference.

Abstract: A method and apparatus are disclosed for controlling the operation of a multiphase motor, and particular to spinning the motor from an inactive state to an operable state. The method and apparatus include initially sensing an electrical characteristic of one or more phase windings, such as performing an inductive sense operation. Having sensed values of the electrical characteristic, a determination is made as to whether or not the motor's rotor is spinning. Upon a determination that the rotor is not spinning, a spin-up operation is performed to bring the spin of the rotor to operable spin speeds. On the other hand, upon a determination that the rotor is spinning, a resynchronization operation is performed to synchronize the application of drive signals for the phase windings of the motor to the dynamic position of the rotor.

Abstract: A communications system, a digital modem and method are provided for reducing non-linear distortion generated by a transmitter which adversely affects a receiver attempting to demodulate received data. More specifically, the digital modem includes a controller that controls a receiver and a transmitter. The receiver is operable to receive a plurality of receiver tones, and the transmitter is operable to generate a plurality of transmitter tones whose intermodulation products (transmitter non-linear distortion) conflict with the plurality of receiver tones. The transmitter is also operable to shift the plurality of transmitter tones by a predetermined distance to move the conflicting intermodulation products off the plurality of receiver tones.

Abstract: Methods and an apparatus for storing information in a processing device with flexible security are disclosed. In one embodiment, an apparatus processes back-to-back write and read operations without stalling the processor. A cache memory subsystem buffers write operations between a central processing unit (CPU) and the cache memory subsystem. Included in the cache memory subsystem are a tag memory, a data memory and a store buffer. The store buffer is coupled to both the data memory and the tag memory. Additionally, the store buffer stores a write operation.

Abstract: A method for forming an aluminum contact through an insulating layer includes the formation of an opening. A barrier layer is formed, if necessary, over the insulating layer and in the opening. A thin refractory metal layer is then formed over the barrier layer, and aluminum deposited over the refractory metal layer. Proper selection of the refractory metal layer and aluminum deposition conditions allows the aluminum to flow into the contact and completely fill it. Preferably, the aluminum is deposited over the refractory metal layer without breaking vacuum.

Abstract: A memory chip which uses a multi-pin port as a JTAG port includes a JTAG controller, at least one internal block and a configuration unit which selectively configures four pins of the multi-pin port to communicate JTAG data to the JTAG controller or to communicate non-JTAG data to the at least one internal block. The configuration unit can be generally permanent or it can be modifiable. For example, the modifiable configuration unit can be a volatile memory (VM) configuration unit or a product term output of a programmable logic device (PLD).

Abstract: The invention provides a method and apparatus for the modulation of more than one channel of audio in a digital amplification system. In the preferred embodiment of the invention, pulse width modulator outputs are staggered in time such that at idle only one channel switches states at a time. This is done to provide an even draw from the power supply, assuming that the same supply is used for the multiple channels. For example, in a two channel system, the idle state of the pulse width modulator for the first channel is 90 degrees out of phase with the pulse width modulator output of the second channel.

Abstract: There is disclosed a field programmable gate array for use in an integrated processing system capable of testing other embedded circuit components in the integrated processing system. The field programmable gate array detects a trigger signal (such as a power reset) in the integrated processing system. In response to the trigger signal, the field programmable gate array receives first test program instructions from a first external source and executes the first test program instructions in order to test the other embedded circuit components in the integrated processing system. When testing of the other embedded circuit components is complete, the field programmable gate array loads its normal operating code and performs its normal functions.

Abstract: A system and method regulates an alternator charging system and includes a memory for storing and regulating voltages used at specific temperatures for the specific alternator charging system requirements of an alternator. A circuit generates a digital signal indicative of both temperature of a battery supplied by the alternator charging system and the charging system voltage. A digital comparator receives the digital signal and compares the digital signal with the regulating voltage stored within the memory for the specific temperature that is indicative of the temperature of the battery supplied by the alternator charging system to generate a regulator control signal.

Abstract: An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.