Abstract: A circuit and method to drive an H-bridge circuit is disclosed. The H-bridge circuit uses NMOS transistors for both the upper and lower sets of transistors. An inductive head is coupled between the terminals of the transistors. When a logic signal is received, it is boosted with a circuit including a capacitor and is used to drive one of the upper transistors. The upper transistor selected to be driven is responsive to the logic signal. A corresponding lower transistor is also driven, forcing current through the inductive head in a first direction. When the logic signal is received that is the complement of the first logic signal, the other upper and lower transistors turn on, thereby driving current through the inductive head in the other direction. Since all of the transistors in the H-bridge circuit are NMOS transistors, boosted driving circuits are used to quickly change the direction of the flux through the inductive head.

Abstract: According to the present invention, by setting the logic state of one or more delay signals to appropriate values, the resistive value of a plurality of power supply delay elements throughout an integrated circuit having distributed circuit blocks may be modified to produce desired delay times or pulse width adjustments throughout the integrated circuit. Setting delay signals to desired logic states may be accomplished by a variety of means including forcing test pads to a logic level, blowing fuses, or entering into a test mode.

Abstract: An SRAM cell includes a pair of N channel transistors acting as inverting circuits, a pair of N channel transistors which perform the control function for the cell, and a pair of N channel thin film transistors in depletion mode with gate and source shorted to provide load devices for the N channel inverter transistors of the SRAM cell.

Abstract: A design for an overvoltage protection circuit can be used to fabricate several different circuits incorporating different protection techniques. The design is suitable for use in a single device, which can be easily and inexpensively packaged and protected from the environment. Three terminal protection circuits can have three terminals on an upper surface of a substrate, or one terminal on a lower surface of the substrate, using a single modular design. Additional circuitry can be included to sense for high current conditions which are caused by overvoltages too low to trigger the normal overvoltage protection circuits.

Abstract: A method and circuit is disclosed for controlling the write head of a magnetic disk storage device. The circuit includes a pull-up device coupled to a terminal of the write head, for selectively providing a current to the write head through the terminal. The circuit further includes parallel-connected first and second current sink circuits, each of which is coupled to the write head terminal and selectively activated to draw current from the write head via the write head terminal. The circuit further includes a control circuit for individually activating the pull-up device and the first and second current sink circuits. In particular, when reversing the direction of current flow through the write head from a first direction in which current is provided to the write head via the write head terminal to a second direction in which current is drawn from the write head from the write head terminal, both the first and second current sink circuits are activated by the control circuit.

Abstract: In a computer system, a processing unit generates a read request and sends it to a cache. If data for the read request is not in the cache, the cache forwards the request to a bus interface unit. If the forwarded request does not fall within the address range of any bus read transaction stored in the bus interface unit, the bus interface unit stores a new bus read transaction corresponding to the forwarded request and sends an identifier for the new transaction to the processing unit. In one preferred embodiment, if the forwarded request falls within the address range of one of the bus read transactions stored in the bus interface unit, the bus interface unit discards the forwarded request and sends an identifier for the one transaction to the processing unit. Additionally, a method of processing read requests is provided. A read request is stored in a buffer and sent to a cache.

Abstract: A method and circuit are disclosed for maintaining stored data within a ferroelectric memory device. The circuit includes a first circuit for selectively logically inverting the data in the ferroelectric memory device. A second circuit enables the first circuit at the one or more predetermined times. A third circuit logically inverts data to be written to and data read from the ferroelectric memory device following every other predetermined time. In this way, the circuit is capable of inverting the data values stored in the ferroelectric memory device, thereby reducing the susceptibility of imprint.

Abstract: An integrated circuit structure and method is capable of automatically tuning the duty cycle of a generated clock signal to any desired value. Tuning of the duty cycle depends upon the precise layout specifications of multiple delay elements of one or more multiplexing circuits of the integrated circuit device. Connecting one or more multiplexing circuits in a serial fashion allows a base frequency to be multiplied in order to produce a generated clock frequency of a desired frequency. Control of select lines to the multiplexing circuits allows the delay path through the one or more multiplexing circuits to be adjusted, thereby automatically adjusting the duty cycle of the generated clock signal.

Abstract: Parallel processing in the form of two PR4 Viterbi Detectors connected in parallel operates to increase the maximum channel speed of a given data channel of a magnetic media. According to a target equation defined as Read(D)=(1−D2)2Written(D), in which D is the delay of a data of the channel, a first Viterbi Detector processes even data samples of the channel that have been equalized according to the target equation and a second Viterbi Detector connected in parallel processes odd data samples of the channel that have likewise been equalized according to the target equation. The use of two parallel-connected Viterbi Detectors in this fashion allows data to be processed at half-rate rather than full-rate, thereby increasing the overall channel speed.

Abstract: Interlevel contacts in semiconductor integrated circuits are fabricated by formation of a contact opening through an insulating layer. A layer of refractory metal, or refractory metal alloy, is deposited over the surface of the integrated circuit chip. An aluminum layer is then deposited at a significantly elevated temperature, so that an aluminum/refractory metal alloy is formed at the interface between the aluminum layer and the refractory metal layer. Formation of such an alloy causes an expansion of the metal within the contact opening, thereby filling the contact opening and providing a smooth upper contour to the deposited aluminum layer.

Abstract: A redundant circuit and method for a semiconductor memory device is disclosed. The redundant circuit includes a programmable circuit for selectively generating at least one first address corresponding to a defective memory row or column line, and shifter circuitry for remapping second addresses which are greater than the first address to row/column lines. For each second address which is greater than the first address, the shifter circuitry remaps the second address to a row/column line which was initially mapped to an immediately higher address relative to the second address. The programmable circuit is capable of generating a plurality of first addresses corresponding to a plurality of defective memory row or column lines.

Abstract: A method of controlling the operations of an on-chip memory unit includes the steps of receiving an indication of at least the ready or busy state of the memory unit and instructing the memory unit to perform the next operation once the indication is of the ready state. The step of receiving can include the repeated steps of capturing the indication and the data and address information of the previous byte provided to the memory unit and shifting the data and address information of a next byte and at least one extra bit through a shift register such that the indication is also shifted out of the shift register to a data out pin of a JTAG port. The steps of capturing and shifting, which provide double buffering, are repeated until the indication is of the ready state. Alternatively, the step of receiving occurs from a non-JTAG port of the chip to a pin on a receiving port. The present invention includes the chip which can operate according to the steps of the method.

Abstract: A system architecture for a high speed serial bus compatible with the 1394 standard is disclosed. A transaction interface coordinates data packets received from or sent to a 1394 bus. A kernel/scheduler/dispatcher is used to allocate memory resources, and start a variety of tasks and services. The tasks and services vary depending on protocols used in a transport layer and application layer used in conjunction with the 1394 layers. Each task operates according to a state machine progression. The transaction interface accepts data information from the tasks and forms data packets for delivery to the 1394 bus. The data packets are initially sent via an associated hardware register, but if busy, the transaction interface polls for other available registers. In addition, all queued transactions are loaded into registers in the most expedient manner.

Abstract: A circuit and method are disclosed for controlling bootstrap circuitry that boosts a voltage level appearing on word lines of a dynamic random access memory device. During execution of a memory access operation, the circuit is adapted to enable the bootstrap circuitry a period of time following the memory device's sense amplifiers initially powering up. The circuit senses when the voltage appearing on a select bit line crosses a predetermined voltage level, and enables the bootstrap circuitry thereafter. In this way, a period of time elapses between the sense amplifiers turning on and the activation of the bootstrap circuitry, thereby reducing noise introduced from the sense amplifiers turning on from impacting the operation of the bootstrap circuitry.

Abstract: An integrated antenna structure wherein a metallic RF antenna provides part of the package structure for an RF transmit/receive chip. The requirement for a separate package to house the driver chip as well as for the wire or cable between the driver chip and the antenna are eliminated. The antenna itself provides a convenient heat sink. This arrangement is particularly attractive at UHF frequencies.

Abstract: An integrated circuit and method are provided for sensing activity such as acceleration in a predetermined direction of movement. The integrated released beam sensor preferably includes a switch detecting circuit region and a sensor switching region connected to and positioned adjacent the switch detecting circuit region. The sensor switching region preferably includes a plurality of floating contacts positioned adjacent and lengthwise extending outwardly from said switch detecting circuit region for defining a plurality of released beams so that each of said plurality of released beams displaces in a predetermined direction responsive to acceleration. The plurality of released beams preferably includes at least two released beams lengthwise extending outwardly from the switch detecting circuit region to different predetermined lengths and at least two released beams lengthwise extending outwardly from the switch detecting circuit region to substantially the same predetermined lengths.

Abstract: A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET reduces the gate coverage of the drain region of the device in order to decrease the device gate to drain capacitance Cgd. A significant portion of the gate overlaying the drain region is eliminated by the removal of a portion of a polysilicon layer that is disposed over a substantial portion of the drain region that resides between the channel portions of the body regions of the device. The resulting open area, that is subsequently covered by an oxide layer, separates the polysilicon gate electrodes of the device. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.

Abstract: A circuit technique to reduce the input capacitance line of a charge integrator is described. This approach is particularly tailored for embedded read-out circuits in solid-state integrated sensors. An integrated charge amplifier described herein includes a generic amplifier element and a high speed buffer which drives a metal shield placed underneath the input line. The metal shield therefore follows the potential of the input line and thereby reduces the capacitance between the input line and ground.

Abstract: A method for starting a polyphase DC motor having a rotor. The position of the rotor is detected by initiating current in each of the phases of the motor and measuring a time period between the initiation of current in the coil and an instant when the current exceeds a threshold current. The phase in which the current reaches the threshold in the shortest amount of time is the phase closest to the position of the rotor. A phase closest to the position of the rotor is identified in each of an odd number of trials, and a starting phase is selected as the phase identified in the majority of trials. The motor is started by providing current to the starting phase.

Abstract: An apparatus and method for underfilling a silicon chip (16) to a substrate (12) by depositing an underfill dam (18) on the surface (20) of the substrate (12) prior to addition of the underfill material (14), is disclosed. A bead of underfill material (14) is provided on the substrate (12) about the periphery of the silicon chip (16), within the underfill dam (18). The underfill material (14) fills the gap (22) between the electrical contacts, the substrate (12) and the silicon chip (16) by capillary action and differential pressure created by a vacuum system (40).