Abstract: A radiation hardened memory device having static random access memory cells includes active gate isolation structures placed in series with oxide isolation regions between the active regions of a memory cell array. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a supply terminal resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.

Abstract: Methods of forming, in an integrated circuit, aluminum-silicon contacts with a barrier layer is disclosed. The barrier layer is enhanced by the provision of titanium oxynitride layers adjacent the silicide film formed at the exposed silicon at the bottom of the contact. The titanium oxynitride may be formed by depositing a low density titanium nitride film over a titanium metal layer that is in contact with the silicon in the contact; subsequent exposure to air allows a relatively large amount of oxygen and nitrogen to enter the titanium nitride. A rapid thermal anneal (RTA) both causes silicidation at the contact location and also results in the oxygen and nitrogen being gettered to what was previously the titanium/titanium nitride interface, where the oxygen and nitrogen react with the titanium metal and nitrogen in the atmosphere to form titanium oxynitride. The low density titanium nitride also densifies during the RTA.

Abstract: A method for fabricating an integrated circuit transistor begins with doping the substrate in the device active areas after field oxide regions have been formed. This dopant helps to reduce short channel transistor effects. A thin layer of epitaxial silicon is then grown over the substrate active regions. A field effect transistor is formed in the epitaxial layer and underlying substrate. The transistor channel region is in the relatively lightly doped epitaxial layer, but the underlying doped substrate layer helps minimize short channel effects.

Abstract: A capacitance sensor detects the absence/presence of physical matter on a sensing surface of the sensor. The capacitive sensor is a multi-cell sensor wherein each cell has one or more buried, protected, and physically inaccessible capacitor plates. The sensor is physically placed in an environment that is to be monitored for deposition of a particle, vapor, and/or drop of a foreign material on the sensing surface. All cells are initially placed in a startup condition or state. Thereafter, the cells are interrogated or readout, looking for a change in the equivalent feedback capacitance that results from an electrical field shape modification that is caused by the presence of physical matter on the sensing surface. When no such change is detected, the method is repeated for another cell. When a change is detected for a cell, a particle/vapor/drop output is provided.

Abstract: A method is provided for forming planar multilevel metallization of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Multilevel metallization is achieved through a planar process at each layer to allow for minimum widths of lines and vias and minimal lateral spacing between lines. Conductive lines and contacts are formed before planarization to further achieve good step coverage. A first metallization layer is formed by depositing aluminum over the integrated circuit, patterning and etching to form metal interconnect lines. Regions of planar insulating material are then formed between the metal lines. Another layer of aluminum is deposited and etched to form metal vias over selected portions of the metal lines. This layer of aluminum is patterned with a reverse pattern of that used to pattern the metal lines. Again, regions of planar insulating material are formed between the metal vias.

Abstract: Disclosed is a CMOS image sensor that includes pixels employing a radiation-sensitive resistive element in which the resistance of the element changes in response to the quantity of radiation striking it. The resistive elements are made from an appropriately doped polycrystalline semiconductor material such as polysilicon. The pixels are provided on a semiconductor device in which the photosensitive resistive elements are provided on a first layer and the pixel associated transistors are provided on a second layer. The fill factor may be approach 100 percent for such pixels.

Abstract: A high impedance load for an integrated circuit device provides an undoped, or lightly doped, layer of epitaxial silicon. The epitaxial silicon layer is formed over a conductive region in a substrate, such as a source/drain region. A highly conductive contact, such as a refractory metal silicide interconnect layer, is formed on top of the epitaxial silicon layer. Preferably, the epitaxial silicon layer is formed using solid phase epitaxy, from excess silicon in the silicide layer, by annealing the device after the silicide layer has been deposited.

Abstract: A method and apparatus for testing a random access memory device, such as a dynamic random access memory device embedded within an integrated circuit chip. The apparatus includes one or more rows of transistors, each of which is connected to a bit line pair of the memory device and to a data line. Data is placed onto the bit lines by driving the data line to a predetermined voltage level and turning on the transistors in the transistor row. Data placed on the bit lines forms a test pattern that may be subsequently written into any row of memory cells. By directly controlling the bit lines of the memory device in this way, test patterns may be quickly and easily stored in the memory device for functional verification thereof.

Abstract: A method is provided of forming a small geometry via or contact of a semiconductor integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to a first disclosed embodiment, an opening is formed partially through an insulating layer overlying a conductive region. Sidewall spacers are formed along the sidewalls of the opening. The remaining insulating layer is etched to expose the underlying conductive region. The contact dimension of the opening is smaller than the opening which can be printed from modern photolithography techniques. According to an alternate embodiment, the opening in the insulating layer expose the underlying conductive region. A polysilicon layer is formed over the insulating layer and in the opening. The polysilicon is oxidized to form a thick oxide in the opening and is etched back to form oxidized polysilicon sidewall spacers which decrease the contact dimension of the opening.

Abstract: An apparatus communicates over a communications channel and has reduced undesired local echo. The transmitter generates a transmit signal to the communications channel in a frequency band outside a voice frequency band. A receiver receives signals from the communications channel within or outside the voice frequency band, and is susceptible to undesired local echo from the transmit signal. In one method, a programmable scaler is connected to the transmitter and generates a scaled replica of the transmit signal based upon a scaled control signal. The receiver is connected to the scaler and reduces the undesired local echo by subtraction of a scaled replica of the transmit signal. An echo reducing circuit senses the received signal power and generates the scaled control signal based upon the received signal power to thereby reduce the undesired local echo In a second method, an estimate of the transfer function from the transmitter digital-to-analog converter to the input of a cancellor is developed.

Abstract: A structure and method for creating an integrated circuit passivation structure comprising, a circuit, a dielectric, and metal plates over which an insulating layer is disposed that electrically isolates the circuit, and a discharge layer that is deposited to form the passivation structure that protects the circuit from electrostatic discharges caused by, e.g., a finger, is disclosed. The discharge layer additionally contains dopants selectively deposited to increase electrostatic discharge carrying capacity while maintaining overall sensing resolution.

Abstract: A method is provided for forming planar multilevel metallization of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Multilevel metallization is achieved through a planar process at each layer to allow for minimum widths of lines and vias and minimal lateral spacing between lines. Conductive lines and contacts are formed before planarization to further achieve good step coverage. A first metallization layer is formed by depositing aluminum over the integrated circuit, patterning and etching to form metal interconnect lines. Regions of planar insulating material are then formed between the metal lines. Another layer of aluminum is deposited and etched to form metal vias over selected portions of the metal lines. This layer of aluminum is patterned with a reverse pattern of that used to pattern the metal lines. Again, regions of planar insulating material are formed between the metal vias.

Abstract: A fault-tolerant code semiconductor memory storage device includes a array of individual multi-level storage devices arranged in a prescribed sequence. A controller is provided for programming the array with sequential data. The controller detects an occurrence of a faulty storage device in the array during a programming of the array with the sequential data. The controller further codes the occurrence of the faulty storage device in a subsequent storage device in the sequence of devices using a fault-tolerant code. A method of fault-tolerant coding of a semiconductor memory storage device is also disclosed.

Abstract: An integrated circuit and method are provided for sensing activity such as temperature variations in a surrounding environment. The integrated released beam sensor preferably includes a switch detecting circuit region and a sensor switching region connected to the switch detecting circuit region. The sensor switching region preferably includes a fixed contact layer, a sacrificial layer on the fixed contact layer, and a floating contact on the sacrificial layer and having portions thereof overlying the fixed contact layer in spaced relation therefrom in an open switch position and extending lengthwise generally transverse to a predetermined direction. The floating contact preferably includes at least two layers of material. Each of the at least two layers have a different thermal expansion coefficient so that the floating contact displaces in the predetermined direction responsive to a predetermined temperature variation so as to contact the fixed contact layer and thereby form a closed switch position.

Abstract: The present application discloses an innovative improved circuit, in which the long transient at write-to-read transitions is avoided by using a shorting switch to short the inputs of the first amplifier stage together when the read amplifier is activated. This speeds up write-to-read transition. Moreover, since read mode can now be entered more quickly after a power-down condition, this circuit also permits the use of other power-saving tricks to idle the read amplifier momentarily.

Abstract: A method and apparatus for reducing the time for determining a memory refresh frequency for a dynamic random access memory. The method includes disabling the bootstrap circuitry associated with a word line when writing data into a memory cell during a test operation. For instances in which data representing a high logic level is written into the memory cell, the resulting charge that is stored is less than the stored charge under normal operation of the dynamic memory. Consequently, the decay time for the stored charge is shortened, thereby shortening the time for testing the refresh frequency of the memory cell. Testing time for the dynamic memory is thus reduced.

Abstract: An H-bridge for applying a current to a coil of a write head assembly for writing data to a magnetic media includes two pair of two switchable transistors. Each pair of transistors is connected between a supply voltage and a reference potential and is adapted to be connected to the coil between the transistors of each pair for turning the transistors turned on and off in a sequence to control the direction of current flow in the coil. The upper transistors of each pair serves a switching transistor, and the lower transistors provide a mirrored referenced current to the coil. A pair of capacitors are connected to a control element of a respective associated one of the lower transistors, and switching circuitry is connected to the capacitors to selectively connect each of the capacitors to inject current into the control element of the respective associated lower transistor when the respective associated lower transistor is turned on.

Abstract: A circuit and method for reconstructing the back emf of a floating coil of a polyphase dc motor in PWM mode is provided. The floating coil is coupled to a first capacitor through a floating phase switch that closes during a pulse produced by the PWM drive signaling the appropriate time to sample in the PWM cycle. The signal on the floating coil is sampled and the sampled signal is stored using a capacitor. After the sampling period, the stored signal is discharged (or charged) at a rate that substantially models the slew rate or slope rate of the expected back emf signal at or near the zero crossing of the back emf signal with the common tap signal. The voltage across the capacitor is a reconstruction of the actual back emf and is generated using samples of the back emf. The reconstructed back emf is compared to the center tap voltage to more accurately detect the zero crossing.

Abstract: A programmable semiconductor contact structure and method are provided. A semiconductor substrate has a first patterned conductive layer for forming an interconnect. A first insulating layer overlies the first patterned conductive layer. An opening is formed through the insulating layer to the first patterned conductive layer to form the contact via. A buffer layer overlies portions of the first insulating layer and covers the opening. A second conductive layer overlies the buffer layer. A third conductive layer then overlies the integrated circuit. The buffer layer is a material, such as amorphous silicon, which functions as an anti-fuse and can be programmed by application of a relatively high programming voltage.

Abstract: A device and method for accessing a row of data in a semiconductor memory device in a single operation is disclosed. The device includes a row of latches having a width which matches the width of the memory array in the semiconductor memory device. The device includes precharge and equilibration circuitry associated with the row of latches and the row of sense amplifiers in device, and timing circuitry for controlling the operation of each in performing full page read and write operations.