Abstract: A socketed integrated circuit packaging system, including a packaged integrated circuit and a socket therefor, is disclosed. The integrated circuit package includes a device circuit board to which a thermally conductive slug is mounted; the underside of the device circuit board has a plurality of lands arranged in an array. The integrated circuit chip is mounted to the slug, through a hole in the device circuit board, and is wire-bonded to the device circuit board and thus to the lands on the underside. The socket is a molded frame, having a hole therethrough to receive the conductive slug of the integrated circuit package; the socket may also have its own thermally conductive slug disposed within the hole of the frame. The socket has spring contact members at locations matching the location of the lands on the device circuit board. The integrated circuit package may be inserted into the socket frame, held there by a metal or molded clip.

Abstract: A technique for testing wordline and related circuitry of a memory array is disclosed. The memory array includes a plurality of memory cells arranged in a plurality of rows, wherein each of the plurality of rows has a respective wordline connected to respective ones of the plurality of memory cells. The related circuitry includes a decode circuit connected to each of the respective wordlines for activating at least one of the respective wordlines based upon a corresponding address signal that is decoded by the decode circuit. The technique involves applying an address signal to the decode circuit so as to activate a corresponding one of the respective wordlines, and then monitoring the corresponding one of the respective wordlines so as to determine if the corresponding one of the respective wordlines has been activated and thereby determine if the memory array and related circuitry are operating in a proper manner.

Abstract: A method is provided of forming a small geometry via or contact of a semiconductor integrated circuit, and an integrated circuit formed according to the same, is disclosed. According to a first disclosed embodiment, an opening is formed partially through an insulating layer overlying a conductive region. Sidewall spacers are formed along the sidewalls of the opening. The remaining insulating layer is etched to expose the underlying conductive region. The contact dimension of the opening is smaller than the opening which can be printed from modern photolithography techniques. According to an alternate embodiment, the opening in the insulating layer expose the underlying conductive region. A polysilicon layer is formed over the insulating layer and in the opening. The polysilicon is oxidized to form a thick oxide in the opening and is etched back to form oxidized polysilicon sidewall spacers which decrease the contact dimension of the opening.

Abstract: A variable capacitor in a semiconductor device is described in which the capacitance is varied by the movement of a dielectric material in the space between the plates of the capacitor in response to an external stimulus. A method of making such a variable capacitor is also described in which the capacitor is built in a layered structure with the top layer including a portion of dielectric material extending into the space between the capacitor plates. After formation of the top layer, an intermediate layer is etched away to render the top layer flexible to facilitate movement of the dielectric material in the space between the capacitor plates.

Abstract: A system and method for reducing noise using recursive noise level estimation. The system and method for noise reduction substitute a target pixel in a processing window with a weighted average of a plurality of neighboring pixels according to the degree of similarity between thc target pixel and the neighboring pixels. The similarity is based on the noise level affecting the image and the local brightness of the processing window. The filter is based on fuzzy logic and filters out noise without smoothing the image's fine details. The filter uses a human visual system (HVS) response to adjust brightness.

Abstract: The present invention provides improved device speed by using two silicides with two different compositions: one silicide is overlaid on a polysilicon gate layer, to form a "polycide" layer with improved sheet resistance, and the other is clad on at least some "active" areas of the monocrystalline silicon, to form a "salicided" active area with improved sheet and contact resistance. Preferably one silicide is a reaction product and the other is deposited.

Abstract: A battery backed-up semiconductor device employs a Vss switching configuration to provide uninterrupted battery power to critical circuitry of the device even in the event of external conditions, such as undershoot, that threaten to corrupt data stored by the device. Both primary power and battery power, when needed, are supplied to floating wells of the device rather than to the device substrate, making the device immune to undershoots that can short the battery to the device substrate and corrupt data stored by the device. The device substrate is permanently tied to the positive power supply voltage and the positive terminal of the battery voltage and is therefore not subject to the concerns associated with switching from a failed primary power supply to the back-up battery power supply.

Abstract: A method of storing a picture in a memory such that the latency of the memory can be reduced when retrieving a picture from the memory to be displayed while still reducing the bandwidth when retrieving an array portion of the picture from the memory, and a memory architecture. The memory is subdivided into a plurality of words for storing a picture having rows and columns. The picture is partitioned into one or more tiles each having a predetermined number of rows and columns. The number of bytes in one row of one tile is equal to the number of bytes in one word, for storing the data in one row of a tile in one word. The chrominance Cr and Cb components can be stored in one word, with the first 8 bytes of the word containing one and the next eight containing the other.

Abstract: A method and circuit for testing a packaged semiconductor memory device allow the acquisition of information on redundant elements by performing one of three possible redundancy rollcall tests on the packaged memory chip. By stimulating the packaged device's pins, the memory chip is set in one of the three test modes. In the first test mode, a preset signal indicating redundancy is sensed and the state of an output pin is changed. In the second test mode, memory array rows are sequentially addressed and the state of an output pin is changed when a redundant row is addressed. In the third test, array columns are sequentially addressed and, when a redundant column is addressed, the state of the output pin to which the redundant column is mapped is changed.

Abstract: A bus interface unit includes a random-access transaction buffer and at least one pointer queue. The transaction buffer stores entries for both in-order transactions and combinable write transactions, and the pointer queue stores pointers to the buffer entries for in-order transactions so as to order the in-order transactions. When a received combinable write transaction has a writing address that falls within the address range of a stored combinable write transactions, the received transaction is merged with the stored transaction. Additionally, a method is provided for processing requested bus transactions. The bus interface unit determines if a requested transaction is a combinable write transaction. If not, address and data information for the requested transaction is loaded into an empty entry in a random-access buffer, and a pointer to that buffer entry is placed in a pointer queue.

Abstract: Silver interconnects are formed by etching deep grooves into an insulating layer over the contact regions, exposing portions of the contact regions and defining the interconnects. The grooves are etched with a truncated V- or U-shape, wider at the top than at any other vertical location, and have a minimum width of 0.25 .mu.m or less. An optional adhesion layer and a barrier layer are sputtered onto surfaces of the groove, including the sidewalls, followed by sputter deposition of a seed layer. Where aluminum is employed as the seed layer, a zincating process may then be optionally employed to promote adhesion of silver to the seed layer. The groove is then filled with silver by plating in a silver solution, or with silver and copper by plating in a copper solution followed by plating in a silver solution.

Abstract: A method is provided for patterning a submicron semiconductor layer of an integrated circuit, and an integrated circuit formed according to the same. An interlevel dielectric layer is formed over the surface of the integrated circuit. A planarizing layer is formed over the interlevel dielectric layer. A photoresist layer is formed and patterned over the planarizing layer. The planarizing layer is etched to form openings exposing selected portions of the interlevel dielectric layer, wherein each opening has the same lateral dimensions. The photoresist and planarizing layers are then removed. The interlevel dielectric layer is etched in the openings to expose portions of the underlying integrated circuit.

Abstract: A method and integrated circuit for providing drive signals to a polyphase dc motor. The integrated circuit is fabricated on a semiconductor substrate for providing drive signals to a polyphase dc motor. The circuit includes a coil drive circuit for connection to drive coils of the motor to selectively supply drive currents thereto in a predetermined sequence. A sequencer circuit commutatively selects the drive coils to which the drive currents are selectively supplied, and a motor, speed controlling circuit controls the speed of the motor by controlling the speed of commutation. A temperature sensing element, such as a diode, is fabricated in the substrate to indicate the temperature of the substrate, and a temperature measuring circuit is connected to the temperature sensing element and to the motor speed controlling circuit to operate the motor speed controlling circuit to slow the speed of the motor when the temperature of the substrate exceeds a first predetermined temperature.

Abstract: A dual landing pad structure is formed with a dielectric pocket. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules.

Abstract: A synchronous counter circuit having a plurality of bit counting stages, each corresponding to a bit position for representing counts, from a least significant bit to a most significant bit. Each bit counting stage includes a flip-flip circuit and a synchronization circuit and each includes circuitry for receiving a pulse train clock signal, synchronously counting said clock signal and outputting an output bit signal corresponding to said counters' stage bit position. The bit counting stages are arranged in two groups, a reset group and a counting group, such that the output bit signal of said flip-flop circuit of the reset group synchronizes data propagation between each bit counting stage of the counting group.

Abstract: A method for starting a polyphase DC motor having a rotor. The position of the rotor is detected by initiating current in each of the phases of the motor and measuring a time period between the initiation of current in the coil and an instant when the current exceeds a threshold current. The phase in which the current reaches the threshold in the shortest amount of time is the phase closest to the position of the rotor. A phase closest to the position of the rotor is identified in each of an odd number of trials, and a starting phase is selected as the phase identified in the majority of trials. The motor is started by providing current to the starting phase.

Abstract: A structure and method for creating an integrated circuit passivation comprising, a circuit (16) over which an insulating layer (26 and/or 28) is disposed that electrically and hermetically isolates the circuit (16) and a silicon carbide layer (30) to form a passivation (24) to protect a circuit (16), is disclosed.

Abstract: A structure and method for creating an integrated circuit passivation (24) comprising, a circuit (16), a dielectric (18), and metal plates (20) over which an insulating layer (26) is disposed that electrically and hermetically isolates the circuit (16), and a discharge layer (32) that is deposited to form a passivation (24) that protects the circuit (16) from electrostatic discharges caused by, e.g., a finger, is disclosed.

Abstract: A radiation hardened memory device having static random access memory cells includes active gate isolation structures placed in series with oxide isolation regions between the active regions of a memory cell array. The active gate isolation structure includes a gate oxide and polycrystalline silicon gate layer electrically coupled to a supply terminal resulting in an active gate isolation structure that prevents a conductive channel extending from adjacent active regions from forming. The gate oxide of the active gate isolation structures is relatively thin compared to the conventional oxide isolation regions and thus, will be less susceptible to any adverse influence from trapped charges caused by radiation exposure.

Abstract: A temperature compensated clock and method of clocking systems are provided. The clock preferably has an oscillator for generating an oscillating waveform signal at a preselected frequency and a frequency divider responsive to the oscillator for dividing the frequency of the oscillating waveform signal. A temperature monitoring circuit is positioned responsive to a voltage input signal independent of temperature and a voltage input signal proportional to temperature for monitoring temperature variations. A temperature compensating circuit, preferably including a programmable scaling circuit, is responsive to the frequency divider and the temperature monitoring circuit for scaling the divided frequency of the generated waveform and thereby advantageously produces a temperature compensated output timing signal.