Abstract: The invention may be incorporated into a method for forming a vertically oriented semiconductor device structure, and the semiconductor structure formed thereby, by forming a first transistor over a portion of a substrate wherein the first transistor has a gate electrode and a source and drain regions. First and second interconnect regions are formed over a portion of the gate electrode and a portion of the source and drain regions of the first transistor, respectively. A source and drain region of a second transistor is formed over the second interconnect. A Vcc conductive layer is formed over a portion of the source and drain region of the second transistor which is formed over the second interconnect.

Abstract: A memory cell with increased resistance to high energy particle radiation. When a memory cell is subjected to high energy particles hit, such as may occur in outer space or in certain harsh environments, design is provided that ensures the data will be maintained in its current state. In particular, a pair of WORD lines access the memory cell such that either WORD line being enabled provides access to the data in the memory cell. The memory cell contains two data storage cells. Each data storage cell contains a pair of cross-coupled transistors which are indirectly cross-coupled to each other via an isolation device. Further, each of the two data storage cells are cross-coupled to each other to reinforce and maintain the data in the respective cross-coupled data storage cell. In the event data is at risk in one of the data storage cells, the other storage cells maintains the data at the correct level at all times.

Abstract: An apparatus (and method) is provided that reduces noise in an embedded DRAM caused by noise in the Vdd supply. A circuit switches or decouples the bit line precharge voltage supply from the memory array to reduce noise in the memory array at time of bit line sensing. In addition, another circuit is utilized to switch or decouple the memory cell plate voltage supply from the memory array to reduce noise in the memory array at the time of bit line sensing. The circuit(s) includes a switch to perform the decoupling, or alternatively, include a switch coupled in parallel with a high impedance.

Abstract: A memory device with a test mode control circuit for entering a test mode responsive to a high on the Vss pin or a low on the Vcc pin that supply power to the output pins during normal operation of the memory device. In test mode the wordlines and bitlines of the memory remain active from the time they are activated, typically when the clock switched from a first to a second logic state, until the clock switches back to the first logic state.

Abstract: A system and method is provided that adds another floating point register set in the floating point execution unit of a microprocessor. Thus, when the floating point state, or environment is stored as an image into memory, it is also stored as a copy in the additional internal registers. When the state, or environment, is to be restored the necessary information (data and/or instructions) is normally present in the additional registers, thus saving CPU cycles by avoiding reloading the image from memory. The present invention allows for either of the two register sets (or a combination thereof) to be, at a given point in time, the working set, with the other being a shadow register set. All of the memory write cycles are monitored (snooped) to determine if the information in the on-chip image has been altered, since the last store operation. The shadowed register file will allow the state of the floating point register file to be kept "as is" on the occurrence of a task switch.

Abstract: A parallel pipelined analog-to-digital converter for use with chips containing large arrays of detectors is described. In these A/D converters, the degree of parallelism decreases between earlier and later pipeline stages. That is, there are fewer instances of at least one of the later stages than there are instances of at least one of the earlier stages. Thus, the instances of the earlier stages are responsible for processing a fewer number of pixels than are instances of the later stages. Viewed another way, the parallel pipelined analog-to-digital converter architecture of this invention assumes a tree or branched arrangement in which the earlier stages correspond to leaves and the later stage condense to branches. In an extreme example, the later stages coalesce to a single route.

Abstract: A DMOS device in a complex integrated circuit having a well region defined by a buried isolation region and an overlapping deep drain region within an epitaxial layer formed over a substrate, a body region having two source regions within the well region, insulated gates over the two source regions, and a Schottky contact over a central portion of the well region and spaced from the body region. The Schottky contact defines a Schottky diode within the epitaxial layer for diverting current from the substrate in the event of a below ground effect or an oversupply effect. The invention reduces or eliminates altogether the effects of parasitic transistors in the complex integrated circuit.

Abstract: A current bias, current sense magneto-resistive preamplifier for a hard disk drive and related methods preferably includes an MR sensor responsive to a current bias for sensing a change in magnetic data flux and responsively providing a change in electrical resistance. A preamplifying circuit is preferably connected to the MR sensor for providing the current bias thereto and for amplifying a detected change in electrical resistance. The preamplifying circuit includes a sensor biasing circuit for providing the current bias to the MR sensor and an amplifying output circuit for providing an amplified output signal representative of the detected change in current bias to the MR sensor. The sensor biasing circuit preferably includes a current source, a first amplifying circuit connected to the MR sensor for sensing the change in electrical resistance therefrom, and a second amplifying circuit having a first input connected to the first amplifying circuit and a second input connected to the current source.

Abstract: An AC and DC input power supply includes an AC power supply circuit and an AC input for receiving a range of AC input voltages. A rectifier circuit is connected to the AC input. An isolation output transformer has first and second primary winding terminals and a low voltage winding section for connecting to a DC voltage input that is lower than the range of the DC voltage that is rectified from the range of AC input voltages. The rectifier circuit is connected to the first primary winding terminal of the isolation output transformer. A transistor is connected to the second primary winding terminal of the isolation output transformer. The DC power supply circuit includes a DC input that is selectably connectable between the first primary winding terminal when the voltage input to the DC input connector is a nominal DC voltage that is within the range of the DC bulk voltage and the low voltage winding section when the voltage input to the DC input is lower than the range of the DC bulk voltage.

Abstract: The a timer circuit and oscillator are disclosed. The timer circuit is similar in functionality to a '555 timer circuit but uses few transistors. The timer circuit has two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter. The two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter are arranged to receive an IN+ voltage, an IN voltage, and a IN- voltage. From these inputs a Q and a Q(bar) output is generated. This timing circuit can be used to generate an oscillator by connecting a capacitor, a current source, and current drain to the IN voltage.

Abstract: A method of operating a memory cell includes detecting a first power supply anomaly or condition. When the first power supply condition occurs, memory cell access to bit lines is disabled, a series of shadow memory access FETs within the memory cells are enabled and data from the memory cells are coupled to memory FETs within the memory cells to store data corresponding to the data from the memory cells in the memory FETs. The memory FETs include nanocrystals of semiconductor material in gate dielectrics of the FETs. Electrons are stored in the nanocrystals of semiconductor material to represent the data stored in the memory cell. When a second power supply condition is detected, the data stored in the memory FETs are written back to the memory cells.

Abstract: An H-bridge circuit having a boost capacitor coupled to the gate of the low-side driver. A driver, in the form of a switching transistor is connected between the load and ground, thus providing a low-side driver. A capacitor is coupled to the gate of the low-side driver to provide a boosted voltage for rapid turn on of the gate. The size of the capacitor selected to be similar to the size of the capacitance associated with the low-side driver transistor.

Abstract: An integrated oscillator and associated methods are provided for providing clock signals. The integrated oscillator preferably includes a micro-mechanical oscillating circuit for providing an oscillating clock signal. The micro-mechanical oscillating circuit preferably includes a support layer, a fixed layer positioned on a support layer, remaining portions of a sacrificial layer positioned only on portions of the fixed layer, and an oscillating layer positioned on the remaining portions of the sacrificial layer, overlying the fixed layer in spaced relation therefrom, and extending lengthwise generally transverse to a predetermined direction for defining a released beam for oscillating at a predetermined frequency. The spaced relation is preferably formed by removal of unwanted portions of the sacrificial layer.

Abstract: An apparatus and method for producing a wrap-around interconnect substrate (60) comprising a substrate (42) having semi-circular vias (62) having openings (64) created by separating through cylindrical vias (62) that were positioned along cutting lines (46a, 46b) that formed part of an integrated circuit substrate strip (40) prior to separation, is disclosed.

Abstract: A multi-head, disc drive, of a data storage system having a preamplifier that is split into a mother chip and set of daughter chips, each daughter chip corresponding to a head in the disc drive. The daughter chips contain very little circuitry, typically just a write driver, the front end of a read amplifier, a write fault detector, and a bias control circuit. Because the daughter chip contains little circuitry, it can be made much smaller and lighter than a conventional preamplifier, allowing the daughter chip to be placed on the suspension, close to the head. This allows the signal sent to and received from the head associated with a daughter chip to be strong enough not to be corrupted during transmission to the circuitry in the rest of the preamplifier. It also increases the bandwidth and reduces the power consumption of the preamplifier. The mother chip contains the remaining circuitry needed in the preamplifier and can be placed farther away, on a portion of the HSA that can support a larger chip.

Abstract: A device for directly loading data onto bit lines of DRAMs. The device eliminates the need for performing a read cycle prior to a write cycle by bypassing the sense amplifiers of the DRAM. An I/O data line is connected to a bit line by a first transmission gate. A second transmission gate is electrically connected between the first transmission gate and the sense amplifier. A voltage level representing a data bit is loaded directly onto a bit line by turning off the second transmission gate to isolate the sense amplifier from the bit line and turning on the first transmission gate to connect the data line to the bit line. The voltage level on the bit line is then stored in a memory cell connected to the bit line.

Abstract: A power supply switching circuit employs hysteresis to ensure stable, timely, and accurate transition between a primary power source and a secondary power source of an integrated circuit. A comparison element of the circuit compares a first voltage signal derived from a primary voltage of the primary power source to a second voltage signal provided by the secondary power source in order to generate a compare output signal. A voltage divider element of the circuit, characterized as having a RC constant, is coupled to the primary power source and receives the compare signal generated by the comparison element and generates the first voltage signal. A bypass element of the circuit is coupled to the voltage divider element and is controlled by the compare signal to bypass the RC constant of the voltage divider element by immediately pulling the first voltage signal to the primary voltage when, after powering up the primary power source, the first voltage signal becomes greater than the second voltage signal.

Abstract: A distance sensor has a capacitive element in turn having a first capacitor plate which is positioned facing a second capacitor plate whose distance is to be measured. In the case of fingerprinting, the second capacitor plate is defined directly by the skin surface of the finger being printed. The sensor comprises an inverting amplifier, between the input and output of which the capacitive element is connected to form a negative feedback branch. By supplying an electric charge step to the input of the inverting amplifier, a voltage step directly proportional to the distance being measured is obtained at the output.

Abstract: A vertical conduction NPN bipolar transistor with a tunneling barrier of silicon carbide in the emitter providing a high emitter injection efficiency and high, stable current gain. The emitter structure comprises a heavily doped polysilicon layer atop a silicon carbide layer that contacts a shallow, heavily doped emitter region at the surface of an epitaxial silicon layer, which is disposed on a monocrystallinie silicon substrate. The silicon carbide layer is about 100 to 200 angstroms thick and has a composition selected to provide an energy band gap in the 1.8 to 3.5 eV range. The thickness and composition of the silicon carbide can be varied within the preferred ranges to tune the transistor's electrical characteristics and simplify the fabrication process.

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.