Abstract: A pair of equivalent controlled impedance buffers are connected in a push-pull configuration to the primary coil of a transformer. A pair of equivalent pre-drivers are connected to the pair of buffers. Each pre-driver receives a driver input signal and outputs a buffer input signal and a flyback compensation signal proportional thereto. Each buffer receives the buffer input signal generated from one of the pre-drivers for buffered output as a line driver signal to the primary coil. A flyback voltage effect is induced in each buffer due to the line driver signal applied to the primary coil by the other buffer. Each buffer further receives the flyback compensation signal generated from the other one of the pre-drivers, with the buffer operating to cancel the flyback voltage effect induced in that buffer by the line driver signal applied to the primary coil by the other buffer using the flyback compensation signal received from the other one of the pre-drivers.

Abstract: A reference voltage generator that may be utilized in an integrated circuit such as a dynamic random access memory (DRAM) includes a voltage divider connected to a voltage supply and a feedback buffer amplifier. The voltage divider, which determines the reference voltage, supplies at least one voltage output signal to the feedback buffer amplifier under control of a feedback control signal supplied by the feedback buffer amplifier. In at least one embodiment, the reference voltage generator further includes a delay element coupled between the voltage divider and the feedback buffer amplifier in-line with the feedback control signal and a low impedance output buffer that receives the voltage output signal from the voltage divider and supplies the reference voltage at an output node. When the reference voltage generator is implemented within a dynamic random access memory, the reference voltage is supplied to the reference plates of bit storage capacitors within the memory cells.

Abstract: A fingertip-operated solid state capacitance switch detects a capacity change that is induced by the physical contact of an ungrounded fingertip to an external dielectric surface of the solid state switch. The input and output of a solid state signal-inverting amplifier are respectively connected to two relatively large and ungrounded capacitor plates that are associated with, but electrically isolated from, the switch's external dielectric surface. An ungrounded fingertip forms a third capacitor plate on the switch's external surface. The solid state amplifier detects the presence of a fingertip on the switch's external surface by way of a change in capacitance within a compound, three plate, capacitor that includes the two ungrounded capacitor plates and the ungrounded fingertip that is resident on the switch's external surface.

Abstract: A method of fabricating an integrated circuit having an n-channel and a p-channel transistor is provided. The method includes forming LDD regions for the n-channel transistors self-aligned to the gate electrodes. A first oxide is then formed over the structure and the n-type silicon regions are implanting with a p+ type dopant through the first oxide to form the source and drain regions of the p-channel transistor. A second oxide is formed over structure. The two oxide layers are then etched to provide sidewall spacers, having an inner portion formed from the first oxide and an outer portion formed from the second oxide. The p-type silicon regions are implanted with an n+ type dopant to form the low resistivity regions of the n-channel transistor. The p+ implants in the source and drain of the p-channel transistor typically outdiffuse toward the gates during further thermal processing of the device.

Abstract: The present invention utilizes a cache which stores various decoded instructions, or parcels, so that these parcels can be made available to the execution units without having to decode a microprocessor instruction, such as a CISC instruction, or the like. This increases performance by bypassing the fetch/decode pipeline stages on the front end of the microprocessor by using a parcel cache to store previously decoded instructions. The parcel cache is coupled to the microprocessor fetch/decode unit and can be searched during an instruction fetch cycle. This search of the parcel cache will occur in parallel with the search of the microprocessor instruction cache. When parcel(s) corresponding to the complex instruction being fetched are found in the parcel cache a hit occurs and the corresponding micro-ops are then sent to the execution units, bypassing the previous pipeline stages.

Abstract: An MOS integrated circuit device with improved electrostatic protection capability includes high and low voltage rails for bringing externally-supplied power to points within the chip. Input bonding pads communicate input signals to the chip from external sources. Clamping circuitry connected to the input bonding pads clamps the input bonding pads to the low voltage rail during an electrostatic discharge event appearing on the input bonding pads. A receiver circuit is coupled to each input bonding pad. Each receiver circuit has a receiver input node, a receiver output node, and overvoltage-sensitive MOS circuitry between the input and output nodes. A conductor connects each input bonding pad to its receiver circuit. The conductor has a length greater than the distance between the input bonding pad and its receiver circuit. The conductor has an inductance sufficient to prevent high frequency components of ESD events received at an input bonding pad from reaching its receiver circuit.

Abstract: An integrated circuit and method are provided for sensing activity such as acceleration in a predetermined direction. The integrated released beam sensor preferably includes a switch detecting circuit region and a sensor switching region connected to and positioned adjacent the switch detecting circuit region. The sensor switching region preferably includes a fixed contact layer, remaining portions of a sacrificial layer on the fixed contact layer, and a floating contact on the remaining portions of the sacrificial layer and having only portions thereof directly overlying the fixed contact layer and in spaced relation therefrom in a normally open position and extending lengthwise generally transverse to the predetermined direction so that the floating contact contacts the fixed contact layer responsive to acceleration in the predetermined direction. The floating contact is preferably a released beam which is released by opening a window or removing unwanted portions of the sacrificial layer.

Abstract: The present invention provides a method for minimizing voids in a plug. The process begins by forming a conformal barrier layer within the hole and then forming a metal plug within the hole. Thereafter, a cap layer is formed over the metal plug in which the cap layer has a lower thermal expansion coefficient than the metal plug. The hole is heated such that the metal in the hole flows to eliminate the void as a result of the compressive stress generated by the cap layer on the metal plug.

Abstract: The device described permits selection between two design options of an integrated circuit by causing a corresponding circuit unit of the integrated circuit to adopt one of two possible different operative states. It comprises an inverter, of which the output terminal is connected to the control terminal of the circuit unit and the input terminal is connected to a first supply terminal by means of a conductor which can be broken by means outside the integrated circuit, and to the second supply terminal by means of a capacitor in parallel with a diode connected for reverse conduction. The device described does not require control signals, takes up a very small area, has practically zero consumption, and can be formed in unlimited numbers on the same integrated circuit.

Abstract: The bond between a flip chip integrated circuit and a substrate is subject to mechanical stress from thermal cycles. This problem is exaggerated when the substrate has a rate of thermal expansion which is appreciably different from that of silicon. This problem is further exaggerated when the IC has a large footprint because it will experience a larger absolute expansion. A solution is proposed to this problem which involves creating an anchoring point. The anchoring point can be in either the IC or the substrate and can be a through-hole or a surface indentation such as a groove or a cutout. The anchoring point is filled with the underfill material during the underfill process. The anchoring point thus provides additional mechanical strength to the bond between the IC and the substrate.

Abstract: The intelligent power supply regulator is used to adjust a supply voltage until an adjusted supply voltage to a served device is at or near the optimal supply voltage of the served device and thereafter maintain the adjusted supply voltage at or near the optimal supply voltage. Depending on the application, the intelligent power supply regulator can comprise: (1) a sensing circuit, a discriminator circuit and a voltage regulating circuit for regulating the supply voltage; or (2) a sensing circuit and a discriminator circuit for controlling a voltage regulating circuit, which regulates the supply voltage. The sensing circuit is coupled to the served device so that at least one performance parameter of the served device can be continuously measured.

Abstract: A high-gain comparator has a built-in hysteresis offset voltage generation feature. The comparator is characterized as having several elements, including a differential amplifier pair that is provided with first and second input voltages, an offset voltage element that creates an offset voltage between the first and second elements of the differential amplifier pair, an output generation element operably coupled to the differential amplifier pair that generates an output voltage of the comparator which is indicative of a voltage difference between the first and second input voltages, and a control element operably coupled to the output signal that controllably adjusts the offset voltage from a first state to a second state in accordance with the output signal to create a hysteresis condition of the comparator.

Abstract: A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET has an increased distance between gate and drain regions of the device in order to decrease the device gate to drain capacitance Cgd. The distance between the gate and drain regions is increased by selective doping of a polysilicon layer of the gate to produce at least two polysilicon gate regions separated by a region of undoped polysilicon that is positioned over a substantial portion of the drain region that resides between the channel portions of the body region of the device. The addition of a contact oxide layer formed directly above the region of undoped polysilicon further increases the distance between gate and drain. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.

Abstract: A bus interface unit includes multiple pointer queues coupled to a random-access transaction buffer. The transaction buffer stores address and data information for each requested bus transaction, and the pointer queues store pointers to the transaction information stored in the transaction buffer. The bus interface unit uses the pointers to order the transactions stored in the random-access transaction buffer. In one preferred embodiment, one pointer queue is used to store pointers for order dependent transactions, and another pointer queue is used to store pointers for non-order dependent transactions. In some embodiments, when an issued transaction is deferred by its target, the deferred transaction's information is maintained in the transaction buffer. Additionally, a method is provided for storing address, data, and ordering information for requested bus transactions. The address and data information for requested transactions is stored as entries in a random-access buffer.

Abstract: A method for synchronously detecting servo information from a data disk includes reading servo information from a disk and passing the servo information signal through a Viterbi detector. The disk is encoded in a known data format from Gray code data to obtain a servo information signal, the encoded Gray code data being constrained to allow no more and no fewer than two “1” states to sequentially occur. The Viterbi detector is modified to eliminate state changes that do not occur within the constrained encoded Gray code data.

Abstract: A method and a circuit for switching a motor controller from pulse width modulation to linear control for a brush-less, sensor-less, poly-phase DC motor. The method includes steps of operating a drive circuit for a poly-phase direct current motor in a pulse width modulation mode and determining that a zero crossing will occur within a predetermined interval. The method also includes steps of enabling a bias current to a transconductance operational amplifier and changing an operating state of the drive circuit from the pulse width modulation mode to a linear mode. The method further includes steps of determining that the zero crossing has occurred, disabling the bias current to the transconductance operational amplifier and changing the operating state of the drive circuit from the linear mode to the pulse width modulation mode.

Abstract: A circuit and method to drive an H-bridge circuit are disclosed. The H-bridge circuit uses NMOS transistors for both the upper and lower sets of transistors. An inductive head is coupled between the terminals of the transistors. When a logic signal is received, one of the upper transistors is driven. The upper transistor selected to be driven is responsive to the logic signal. A corresponding lower transistor is also driven, forcing current through the inductive head in a first direction. The driving circuit for the lower transistors includes a programmable circuit structured to capacitively couple the output of the driving circuit to a pull-up voltage, thereby allowing the amount of current forced through the inductive head to be maximized for optimum data transfer. Within the programmable voltage boost circuit are several logic gates, each coupled to a capacitor of differing value.

Abstract: A field-effect transistor and a method for its fabrication are described. The transistor includes a monocrystalline channel region extending from a monocrystalline body region of a semiconductor substrate. First and second source/drain regions laterally adjoin opposite sides of the channel region and are electrically isolated from the body region by an underlying first dielectric layer. The source/drain regions include both polycrystalline and monocrystalline semiconductor regions. A conductive gate electrode is formed over a second dielectric layer overlying the channel region. The transistor is formed by selectively oxidizing portions of a monocrystalline semiconductor substrate and then removing portions of the oxidized substrate. The resulting structure includes a body region of the substrate having overlying first and second oxide regions, with a protruding channel region extending from the body region between the oxide regions.

Abstract: A method and an apparatus are provided for communicating data in noisy environments. A method preferably includes communicating a first fixed data signal at a first frequency on a first data communications line and communicating a second data signal at a second frequency on a second data communications line. The second frequency is preferably correlated to the first frequency by a predetermined coefficient so as to define a correlation value between the first and second data signals. The correlation value preferably represents a predetermined function. The method also preferably includes determining the correlation value responsive to the first and second data signals. The method can also advantageously include communicating a third data signal at the second frequency on the second data communications line. The third data signal is preferably phase shifted from the second data signal.

Abstract: An improved transistor package with superior stability to wave soldering, having a nickel oxide barrier strip formed on the surface of the leads.