Abstract: Composite layers of titanium silicide and polysilicon define a fuse resistor within a programmable fuse element that increases its resistance from about 50 ohms in the unprogrammed state to about 250 K-ohms in the programmed state by creating a discontinuity in the silicide layer immediately over a PN junction in the polysilicon layer. The resistance of the fuse resistor in the programmed state is determined by the reverse-biased diode characteristic of the PN junction. Portions of a metallic layer overlie portions of the fuse resistor except at the site of the PN junction in the polysilicon layer so that the silicide is preferentially heated immediately above the PN junction to cause the discontinuity to occur at that site. The metallic layer portions serve both as a heat sink for the underlying portions of the silicide layer and as electrical connections to the fuse resistor.

Abstract: A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET reduces the gate coverage of the drain region of the device in order to decrease the device gate to drain capacitance C.sub.gd. A significant portion of the gate overlaying the drain region is eliminated by the removal of a portion of a polysilicon layer that is disposed over a substantial portion of the drain region that resides between the channel portions of the body regions of the device. The resulting open area, that is subsequently covered by an oxide layer, separates the polysilicon gate electrodes of the device. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.

Abstract: A method of forming an isolation region in an integrated circuit and an integrated circuit formed thereby. A method preferably includes forming at least one trench in a semiconductor substrate, forming an insulation layer of material in the at least one trench and on peripheral regions of the at least one trench of the semiconductor substrate, forming a sacrificial layer of material on the insulation layer having a different polishing rate than the insulation layer, and polishing the layer having the different polishing rate and portions of the insulation layer so that the sacrificial layer having the different polishing rate and portions of the insulation layer are removed, so that other portions of the insulation layer remain in the at least one trench of the substrate, and so that the upper surface of the at least one trench and the peripheral regions thereof in combination provide a substantially planar surface.

Abstract: A circuit and method for clocking counters in a polyphase dc motor is provided in which the motor is capable of operating at two or more operating states, spin-up and regulation. The system clock is connected to the clocking circuit through dividers to produce a first clock signal having a low frequency for operating the counter at spin-up, and a second clock signal having a higher frequency for operating the counter at regulation. The clocking circuit includes a switch for connecting the first clock signal to the clock input of the counter when the motor is at spin-up, and for connecting the second clock signal to the clock input when the motor is at regulation. The switch is controlled by a switch control circuit that ensures that switching does not occur when the counter is timing the motor by only allowing the switching to occur when the counter is at an end of a timing cycle and before the counter resets. An at-speed circuit is used to determine whether the motor is at spin-up or at regulation.

Abstract: A method and a circuit for controlling a slew rate of a coil in a voice coil motor in a disk drive system. A slew rate control signal is generated by a microprocessor or by an analog circuit in response to one or more operating parameters of the disk drive system. A driver circuit selectively couples the coil between a voltage source and a ground in response to a driver signal, and controls the slew rate of the coil in response to the slew rate control signal.

Abstract: A semiconductor integrated circuit comprises a substrate including a plurality of transistors, and a conductive line for coupling at least two of the transistors with each other, each transistor comprising a drain diffusion region, a source diffusion region, a gate region, and a test diffusion region within the substrate, the test diffusion region being electrically coupled to a metal line within the semiconductor integrated circuit for establishing an indication of the voltage at the probing diffusion region.

Abstract: A power supply switching circuit ensures stable, timely, and accurate transition between a primary power source and a secondary power source of an integrated circuit. A comparison element of the circuit compares a first voltage signal derived from a primary voltage of the primary power source to a second voltage signal, also derived from the primary voltage but having a different rate of change than the first voltage signal, to generate a compare output signal. The first and second voltage signals are characterized as being equal to each other when the primary voltage is equal to a predetermined crossover point at which the integrated circuit device will be powered by the primary voltage.

Abstract: A low/zero power memory device includes a deselect mode of operation wherein row decoders, column decoders, write decoders, pre-coders, post-coders and like operational circuits of the memory device needed for wordline and column activation are disabled until such time as a memory device supply voltage exceeds a certain threshold. An included test mode circuit detects test mode activation and overrides application of the power fail deselect mode of operation of the device. This activates the wordline and column related operational circuits immediately at power up such that the device powers up with multiple wordlines and columns activated and ready for application of a stress test overvoltage.

Abstract: A circuit and method for measuring a back EMF voltage of a voice coil in a mass storage device, or the like, includes an amplifier connected across the coil to produce an output signal proportional to a voltage across the coil and a circuit connected to selectively connect the output signal of the amplifier to a circuit output when a driving current is not applied to said coil. A sample window is generated after drive currents within the coil have been allowed to decay to zero, and between a time during which a PWM signal changes from negative to positive and a time when the PWM waveform crosses a voltage error value.

Abstract: Method and system for monitoring a plasma etch process performed in a plasma processing chamber, the method and system being capable of accurately monitoring and controlling the plasma etch process without being affected by the change in a plasma light emission transmission characteristically caused by process polymer depositions on a detecting surface or sampling window.

Abstract: An integrated circuit and associated method for switching from a power supply to a battery are provided. The integrated circuit preferably includes a memory circuit responsive to an external power supply and to a battery for storing data therein and a sleep mode latching circuit connected to the memory circuit for latching the memory circuit in a reduced power sleep mode condition so as to reduce power usage of a battery and a non-sleep mode operating condition so as to allow normal operation of the memory circuit by a power supply. The integrated circuit preferably also includes a sleep mode latch locking circuit connected to the sleep mode latching circuit and the memory circuit and responsive to a power supply for locking the sleep mode latching circuit in the non-sleep mode operating condition when power supplied from the power supply falls below a predetermined threshold so that the memory circuit is inhibited from inadvertently entering the reduced power sleep mode condition.

Abstract: A memory, such as a static random access memory (SRAM), includes at least one memory cell. The bit lines for that memory cell are selectively connected to corresponding write bit lines through a column select pass transistor and a selectively blowable fuse. A reset circuit is connected to the same write bit lines through a fuse structure mimic circuit. Responsive to data transitions on the write bit lines, the reset circuit operates to detect the occurrence of a memory operation to the memory cell and generate a reset signal for resetting the memory in preparation for a next write operation. To support substantially simultaneous presentation of write data to both the reset circuit and the memory cell, the fuse structure mimic circuit delays presentation of the write bit line data to the reset circuit.

Abstract: A low-voltage high-current discrete insulated-gate field-effect transistor which is made by a very economical process with two silicon etches. A buried poly gate gates conduction along a trench sidewall. The channel is provided by the residuum of an epi layer, and the source diffusion is provided by an unmasked implant which is screened only by various grown oxides.

Abstract: A dynamic random access memory (DRAM) circuit is provided that utilizes a testing system and method to determine the sensitivity of a sense amplifier. More specifically, the DRAM circuit, in determining the sensitivity of the sense amplifier, utilizes a testing system to independently control the magnitude of a voltage differential appearing between a pair of bit lines and sensed by the sense amplifier. The sensitivity of the sense amplifier is then able to be determined by monitoring an input/output signal in response to sensing the known voltage differential. The testing system controls the magnitude of the voltage differential appearing between the bit lines by enabling a first dummy cell to transfer a first reference charge onto a first bit line and by enabling a second dummy cell to transfer a second reference charge onto a second bit line.

Abstract: An apparatus and method for controlling the height of packaging above an integrated circuit package (30) comprising, a substrate (12), a silicon chip (16) and a signal wire (20), one or more height detection wires (32) extending above the top surface (26) of the silicon chip (16) and the signal wire (20) and a detector electrically connected to the height detection wire (32), wherein the height detection wire (32) and the detector form an electric circuit that is affected when a polisher of encapsulant (40) is in proximity to the height detection wire (32), is disclosed.

Abstract: A method of parking the head by first moving the head toward the inner diameter of the disc an then back across the disc and parking the head on a flat part of a ramp. In one embodiment, a moderate voltage on the motor drives the head toward the inner diameter of the disc until the head hits the inner crash stop and then a moderate current drives the head back across the disc to give the head enough momentum to get to the flat part of he ramp. In another embodiment, more stages, each having a different voltage, are used to get better control of the velocity of the head as it is being driven across the disc. A higher voltage is also used to turn the head to move toward the inner diameter of the disc when it is moving fast toward the outer diameter. A retract circuit controls the movement of the head during retract. To be able to drive the head in the tow directions, the retract circuit needs to be bipolar, containing both a current source and a current sink. Counters are used to time the driving of the head.

Abstract: A method for fabricating an integrated circuit transistor begins with doping the substrate in the device active areas after field oxide regions have been formed. This dopant helps to reduce short channel transistor effects. A thin layer of epitaxial silicon is then grown over the substrate active regions. A field effect transistor is formed in the epitaxial layer and underlying substrate. The transistor channel region is in the relatively lightly doped epitaxial layer, but the underlying doped substrate layer helps minimize short channel effects.

Abstract: A motor control circuit control the operation of a motor that includes a motor coil. The motor control circuit includes an analog driver structured to supply the motor coil with a supply voltage in response to receiving an analog driver input signal. Coupled to the analog driver is a digital-to-analog converter that is structured to convert a digital motor control signal to the analog driver input signal. Coupled to the digital-to-analog converter is a lever shifter that is structured to receive a low voltage digital command signal from a digital motor controller. The level shifter is also structured to increase the voltage of the digital command signal to produce the digital motor control signal and provide the digital motor control signal to the digital-to-analog converter.

Abstract: An integrated circuit structure and method provides for an integrated circuit device to respond to an edge transition detection (ETD) pulse in one of two ways. First, in response to the ETD pulse, the integrated circuit device exits a test mode at least temporarily every cycle of the integrated circuit device. Second, a node of the integrated circuit device is re-initialized every cycle if it is not forced by a super voltage indicative of test mode entry. Both of these responses prevent accidental entry of the integrated circuit device into the test mode. If the integrated circuit device is supposed to be in the test mode, it stays in the test mode. If, however, the integrated circuit device is not intended to be in the test mode, the ETD pulse forces the integrated circuit device out of the test mode. Subsequent entry into the test mode of the device is permitted if conditions for entry into the test mode have otherwise been met.

Abstract: An integrated circuit and method are provided for sensing activity such as acceleration in a predetermined direction of movement. The integrated released beam sensor preferably includes a switch detecting circuit region and a sensor switching region connected to and positioned adjacent the switch detecting circuit region. The sensor switching region preferably includes a plurality of floating contacts positioned adjacent and lengthwise extending outwardly from said switch detecting circuit region for defining a plurality of released beams so that each of said plurality of released beams displaces in a predetermined direction responsive to acceleration. The plurality of released beams preferably includes at least two released beams lengthwise extending outwardly from the switch detecting circuit region to different predetermined lengths and at least two released beams lengthwise extending outwardly from the switch detecting circuit region to substantially the same predetermined lengths.