Abstract: A disc drive apparatus and a method for synchronizing information components read from a compact disc media are described. The method includes selecting a start minutes/seconds/frames MSF for a data component and triggering a transfer of the data component to a buffer when the start minutes/seconds/frames for the data is detected. The method also includes selecting a start minutes/seconds/frames for a subcode component and triggering a transfer of the subcode component to the buffer when the start minutes/seconds/frames for the subcode is detected. A buffer manager monitors the contents of the buffer and counts the data and subcode components through separate counters. The buffer manager releases the data component and the subcode component to a host from the buffer when synchronization of the data component and the subcode component is detected.

Abstract: A technique for forming integrated circuit device contacts includes the formation of nitride spacers along side gate electrodes for LDD definition. In addition, a nitride cap layer is formed over the gate electrodes. When a contact opening is formed through the interlevel oxide dielectric, the nitride cap and sidewall spacers protect the gate electrode from damage and shorting. A highly doped poly plug is formed in the opening to make contact to the underlying substrate. Metalization is formed over the poly plug in the usual manner.

Abstract: A frequency test circuit (200) includes a built-in self test (BIST) circuit (212) which provides for testing of a frequency generating circuit such as an oscillator circuit (100). The test circuit (200) includes circuit stages (202-208) which help produce a reference signal (210) which has substantially the same frequency as that produced by the oscillator circuit (100) when it is operational. Since the low current oscillator circuit (100) can fail at any one of the divider or level shifting stages (106-112), the test circuit (200) can determine if the reference signal and the output signal of the oscillator have substantially the same frequency and produce a test condition signal indicative of either a pass or failed test at test port (214).

Abstract: An electronic system provides direct access between a first device and a decoder/encoder and a memory. The electronic system can be included in a computer in which case the memory is a main memory. Direct access is accomplished through one or more memory interfaces. Direct access is also accomplished in some embodiments by direct coupling of the memory to a bus, and in other embodiments, by direct coupling of the first device and decoder/encoder to a bus. The electronic system includes an arbiter for determining access for the first device and/or the decoder/encoder to the memory for each access request. The arbiter may be monolithically integrated into a memory interface of the decoder/encoder or the first device. The decoder may be a video decoder configured to decode a bit stream formatted to comply with the MPEG-2 standard. The memory may store predicted images which are obtained from a single preceding image and may also store intra images.

Abstract: An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells.

Abstract: A method and apparatus, for applying a current to a coil of a write head assembly of a disk drive, or the like, to cause the flux within the coil to rapidly reverse, has an H-bridge having two pair of two switchable transistors. Each pair of the transistors is connected between a supply voltage and a reference potential, and is adapted to be connected to the coil between the two transistors of each pair. The two transistors of the first pair may be connected to receive a control signal to turn on complementary transistors of the first and second pair of transistors to selectively control current flow in the coil in first or second directions. A reference current source supplies a reference current, and one of the transistors in each of the first and second pairs of transistors is connected when turned on to mirror the reference current to control the currents in the coil.

Abstract: A VDMOS structure with an added n- doping component, and a LOCOS oxide self-aligned to it, at tie surface extension of the drain. The additional shallow n- component permits the body diffusion to be heavier, and hence reduces the risk of latchup.

Abstract: A method is provided for forming an isolation structure at a semiconducting surface of a body, and the isolation structure formed thereby. A masking layer is formed over selected regions of the substrate surface; the masking layer preferably comprising a nitride layer overlying a pad oxide layer. The masking layer is patterned and etched to form openings exposing selected regions of the substrate surface. Recesses are formed into the substrate in the openings. Preferably a portion of the pad oxide layer is isotropically etched under the nitride layer forming an undercut region. An etch stop layer is formed over the substrate in the recesses filling in the undercut along the sidewalls. A second masking layer, preferably of nitride is formed over the etch stop layer and anisotropically etched to form nitride sidewalls in the openings. The etch stop layer may be etched away from the horizontal surfaces.

Abstract: A memory device includes an array of floating gate FET memory cells capable of storing either analog or digital data. The memory device includes first read-write circuitry for storage and retrieval of digital data, and second read-write circuitry for storage and retrieval of analog data. As a result, the digital data storage capability facilitates real-time operation of devices using the memory device without sacrificing the memory capacity capabilities of analog data storage. When a host device using the memory device is not in use, the stored digital data may be read out from the memory device, converted to analog form and then stored in the memory device, re-capturing the data density capabilities of analog data storage in floating gate FET memory cells.

Abstract: A method and a circuit for correcting asymmetry in a response signal generated by a magneto-resistive head. The magneto-resistive head generates a response signal to transmit digital information read from a magnetic media storage device. The asymmetry is corrected in a negative feedback manner by squaring an output signal, modulating the squared output signal, and subtracting the modulated squared output signal from the response signal to generate the output signal. The circuit employs a differential amplifier as an input stage and a Gilbert multiplier circuit to square the output signal.

Abstract: A precision analog circuit ensures precision matching between two or more resistive elements. In order that the two or more resistive elements are truly matched, a first electrical value, such as V.sub.DS, of the two or more resistive elements are equal and a second electrical value, such as V.sub.GS, of the two or more resistive elements are equal so that a ratio of the first resistive element to the second resistive element is a predetermined value regardless of the voltage coefficients of the resistive elements.

Abstract: A circuit and method are provided for generating an initializing signal to a master enable fuse circuit on a redundant line decoder. An initialization pulse may be applied to a master enable circuit having a master enable fuse. The master enable fuse may be coupled to a switched voltage supply powered selectively by battery voltage and external Vcc. A circuit for generating the INITIAL signal determines the transition from a power down state to a powered state. A series of delay elements in a generating circuit generates a predetermined initialization pulse of around 3 ns to 5 ns. Half-latch circuits may be initialized between a first and second voltage threshold. Accordingly, the master enable circuits may be set to the proper initialization states for proper operation and minimum power consumption.

Abstract: The present invention is directed to an improved deep trench structure, for use in junction devices, which addresses junction breakdown voltage instabilities of the prior art. The primary, or metallurgical, junction where avalanche breakdown occurs is moved away from the surface dielectric into the bulk silicon by adding a lightly doped layer adjacent to the deep trench. A preferred embodiment suitable for isolated structures places the doped layer adjacent to the sidewalls of the deep trench. A second preferred embodiment, suitable for non-isolated structures, places the doped layer adjacent to both the floor and the sidewalls of the trench.

Abstract: A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type disposed on a surface thereof and a dielectric layer including silicon nitride disposed on the surface. The dielectric layer includes openings at least partially disposed on the p-wells. The dielectric layer also includes a top latter comprising silicon dioxide having a thickness of less than ten angstroms. Trenches having a depth comparable to or greater than a depth of the wells extend into the substrate surface within the openings. A nonconductive material is disposed within the trenches and has an upper surface that is substantially coplanar with the dielectric layer. Portions of the dielectric layer are used as gate dielectrics for transistors.

Abstract: A method for fabricating polycrystalline silicon resistor structures includes steps directed to the provision of a polycrystalline silicon structure having a decreased width. In one embodiment, sidewall spacers are used to narrow a region in which the polycrystalline silicon resistors are formed. In an alternative embodiment, polycrystalline silicon resistors are formed as sidewall structures in a resistor region. Use of either technique provides a reduced cross-section for the resistor structures, allowing shorter resistors to be used, or providing increased resistance for longer resistors.

Abstract: A timer circuit and oscillator are disclosed. The timer circuit is similar in functionality to a '555 timer circuit but uses few transistors. The timer circuit has two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter. The two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter are arranged to receive an IN+ voltage, an IN voltage, and a IN- voltage. From these inputs a Q and a Q(bar) output is generated. This timing circuit can be used to generate an oscillator by connecting a capacitor, a current source, and current drain to the IN voltage.

Abstract: A multiplexing circuit includes a reference terminal, a plurality of multiplexing input terminals, and a buffer having an input terminal and an output terminal. The multiplexing circuit also includes a plurality of first elements that each have a programmable conductivity and that are each serially coupled between a corresponding one of the multiplexing input terminals and the input terminal of the buffer. When one of the input signals is to be coupled to the multiplexer output terminal, the element corresponding to the selected input signal is programmed in a conductive state, and the remaining elements are programmed in a nonconductive state. When none of the input signals are selected, each element is programmed in a conductive state and the input signals each have the same value so as to prevent signal conflicts and short circuits at nodes within the multiplexing circuit.

Abstract: An integrated circuit structure and method provides a burn-in stress test mode that facilitates stress testing of an integrated circuit device in a burn-in oven. The integrated circuit structure and method is capable of disabling a time-out feature of an IC memory device during a stress test mode of the device in order to facilitate stress testing of the device in a burn-in oven. The integrated circuit structure provides for entry into the burn-in stress test mode when a supply voltage supplied to the integrated circuit device exceeds a predetermined voltage level and/or the temperature of the integrated circuit device exceeds a predetermined temperature level.

Abstract: An MOS integrated circuit device with improved electrostatic protection capability includes high and low voltage rails for bringing externally-supplied power to points within the chip. Input bonding pads communicate input signals to the chip from external sources. Clamping circuitry connected to the input bonding pads clamps the input bonding pads to the low voltage rail during an electrostatic discharge event appearing on the input bonding pads. A receiver circuit is coupled to each input bonding pad. Each receiver circuit has a receiver input node, a receiver output node, and overvoltage-sensitive MOS circuitry between the input and output nodes. A conductor connects each input bonding pad to its receiver circuit. The conductor has a length greater than the distance between the input bonding pad and its receiver circuit. The conductor has an inductance sufficient to prevent high frequency components of ESD events received at an input bonding pad from reaching its receiver circuit.

Abstract: A control circuit for terminating a memory access cycle in a memory block having at least one memory cell is disclosed. The at least one memory cell has unique process characteristics. The control circuit includes a memory block activation circuit for generating a memory block activation signal. The memory block activation circuit includes a reset circuit for terminating the memory block activation signal when activated. The control circuit also includes a memory access cycle tracking circuit, responsive to the memory block activation signal, for generating a reset signal. The memory access cycle tracking circuit includes the unique process characteristics of the at least one memory cell for tracking an operation of the at least one memory cell. The reset signal activates the reset circuit so as to terminate the memory block activation signal and terminate the memory access cycle in the memory block.