Abstract: A master-slave D type flip-flop circuit includes a power consumption circuit including a reference stage in parallel with a master and a slave stage of the flip-flop circuit. This structure advantageously provides a switching of the flip-flop circuit on each of the leading and trailing edges of the clock signal for the sequencing of the flip-flop circuit.

Abstract: A interconnection structure of the damascene type is produced on a surface of a microelectronic device that includes at least one dielectric material layer for housing at least one interconnection and at least one interface layer on the dielectric material layer. The interface layer may include at least one SiCH layer and at least one SiOCH layer.

Abstract: A method is provided for generating a pulse signal with modulable-width pulses. A set-point signal is generated and compared with a control signal so as to produce the pulse signal. When the control signal is a two-state logical signal, a first reference voltage is taken as the set-point signal. When the control signal is a continuous analog voltage, the set-point signal is varied between the first reference voltage and a predetermined second reference voltage, which is higher than the first reference voltage. Also provided is a device for generating a pulse signal with modulable-width pulses. The device includes a set-point signal generator, a control signal generator, and a comparator that outputs the pulse signal. The set-point signal generator includes a first voltage source for generating a first reference voltage, and a second voltage source for generating a second reference voltage, which is higher than the first reference voltage.

Abstract: A method of integrated circuit assembly before encapsulation including at least one step of soldering, under mechanical pressure, a first element on a second element, including temporarily maintaining a predetermined spacing, at least partially without solder paste, between the surfaces to be assembled of the first and second elements.

Abstract: A method of removal of polymers of the type including bromine, chlorine, silicon, and carbon, present on a semiconductor wafer partly covered with resist, including of rotating the wafer in its plane around its axis, in an enclosure under a controlled atmosphere, at ambient temperature, including the steps of rotating the wafer at a speed included between 500 and 2000 CPM in an enclosure filled with nitrogen; sprinkling the wafer with water, substantially at the center of the wafer; introducing hydrofluoric acid during a determined cleaning time, while maintaining the sprinkling; and rinsing the wafer by continuing the sprinkling to remove any trace of hydrofluoric acid from the wafer, at the end of the cleaning time.

Abstract: The present invention relates to a device of protection of a monolithic component including a MOS-type vertical diffused power transistor formed of a great number of identical cells, and a measurement transistor formed of a smaller number of cells identical to those of the power transistor, the drains and the gates of all cells being common, an inductive load being connected to the source of the power transistor, a short-circuiting circuit connected between the source of the power transistor and the source of the measurement transistor, and a control circuit that turns on the short-circuiting circuit when the power transistor turns off.

Abstract: A secured electrically modifiable non-volatile memory includes a circuit to determine if memory cells therein have been exposed to ultraviolet radiation. The memory includes at least one additional memory cell, called a reference cell, and an associated read circuit for detecting any erasure of the reference cell by ultraviolet radiation. At each access to the memory, the reference cell is read by the associated read circuit. If the state of the reference cell is different from its initial electrical state, then operation of the memory is stopped.

Abstract: With a switch including at least one insulated-gate field-effect transistor, an analog input signal is delivered on the source of the transistor and the transistor is controlled on its gate synchronized with a clock signal to successively turn it on and off. On the conclusion of each half-period of the clock signal during which the transistor is off, a precharging capacitor is precharged at the start of the next half-period and for a predetermined precharge duration, with a predetermined precharge voltage. Then, for the remaining duration of the half-period, the precharged capacitor is connected between the source and the gate of the transistor to turn it on under the action of a gate-source voltage which is almost independent of the level of the input signal. At the end of the half-period, the gate of the transistor and the precharging capacitor are grounded.

Abstract: In an electronic component including a two-way bus through which data elements travel between peripherals and a central processing unit at the rate of a clock signal, the central processing unit and at least one of the peripherals each includes a data encryption/decryption cell. Each data encryption/decryption cell uses the same secret key. The secret key is produced locally at each clock cycle in each cell from a random signal synchronous with the clock signal, and is applied to each of the cells by a one-way transmission line.

Abstract: The present invention relates to an integrated circuit test pad implemented in a surface metallization layer covered with an insulating coating. The pad is surrounded with a first metal ring made in the surface metallization layer and with a second metal ring made in a lower metallization surface, the first and second rings being electrically interconnected by at least one via and set to a fixed potential.

Abstract: A circuit for detecting the disappearing of a periodic input signal, the circuit including a frequency divider receiving the input signal, the frequency divider having two complementary outputs combined with a same reference signal of same frequency as the input signal by means of two respective similar logic gates, the output of a first one of the logic gates being connected to increment a first counter and to reset a second counter similar to the first one, and the output of the second logic gate being connected to increment the second counter and to reset the first counter, and a logic circuit generating a disappearing detection signal when any one of the two counters reaches a predetermined value.

Abstract: A processor that includes an instruction extraction stage, an instruction register, an instruction decoder, a first multiplexer that supplies the instruction register, and an autonomous counter with a presetting register. The first multiplexer receives the output of the extraction stage and the output of the instruction register, and the instruction decoder receives the output of the instruction register. Additionally, a first circuit produces a repetition signal if a received instruction is a repetition instruction, and a second circuit outputs a value from the received instruction to the presetting register when the received instruction is a repetition instruction. A third circuit produces an instruction execution signal that is supplied to the counter, and the first multiplexer is controlled so as to supply the instruction register based on a control output of the counter. The present invention also provides a method of handling instructions to be repeated by a processor.

Abstract: A converter of a high A.C. voltage into a low D.C. voltage, including a one-way switch between a first terminal of application of the A.C. voltage and a first positive output terminal, and circuitry for controlling the output voltage to a desired value, the one-way switch being controlled in linear mode.

Abstract: A negative load pump circuit includes switching MOS transistors and capacitors. Each switching transistor is formed in a well on an integrated circuit, and each transistor has its well contact or body connected to its gate and to its source to receive a phase signal. The device advantageously includes a circuit for the regulation of the negative load pump circuit. This maintains the negative load pump circuit in stopped conditions corresponding to minimum power consumption, and enables a speedy supply of a negative low level expected at the output of the negative load pump circuit for an intended application. This is based upon activation by an external command.

Abstract: A method for characterizing a structure including single-crystal silicon-germanium areas on a single-crystal silicon substrate, including the steps of measuring the X-ray diffraction spectrum of the structure, simulating the diffraction spectrum of a single-crystal silicon substrate, simulating the diffraction spectrum of a single-crystal silicon substrate entirely coated with a single-crystal SiGe layer, adding the simulated spectrums while assigning them weights a and 1-a to obtain a sum spectrum, comparing the sum spectrum with the measured spectrum and adjusting the simulation parameters and weight a to reduce the distance between the sum spectrum and the measured spectrum, and after optimizing, adopting the simulation parameters as the measurement parameters.

Abstract: The parameter J0 associated with the implementation of modular operations according to the Montgomery method is generated in an integrated circuit. J0 is encoded on Q*L bits such that J0=J0Q−1 . . . J00, wherein Q and L are integers. Loops are formed for the computation of the binary data elements J0j according to a known method, which is used for generating the sub-operands of L bits. A coprocessor is used for updating, by multiplication, of the value of a data element of Q*L bits of which the L least significant bits are used for the computation of the values of J0j.

Abstract: A primary circuit produces an internal resetting signal as a function of two input signals: an external resetting signal and a clock signal internal to the microprocessor. Depending on the characteristics of these two input signals, the internal resetting signal is generated according to a synchronous or an asynchronous mode. Generation of the internal resetting signal is delayed when the selection signal corresponds to the synchronous resetting mode.

Abstract: The present invention relates to an integrated circuit, at least one portion of which includes at least one group of standby cells for possible connection to said portion of the integrated circuit by replacement connections, the length of which cannot exceed a predetermined value. The inputs and outputs of the standby cells are connected to metal standby tracks being disposed on the circuit such that any node of the circuit portion is distant by at most said predetermined value from any point on the tracks.

Abstract: A method for testing whether an antenna circuit of a contactless chip card is defective. The antenna circuit is an inductive resonant circuit comprising a capacitor and an antenna coil. The antenna coil of the resonant circuit is excited by inductive coupling using a test coil wherein the excitation is then sharply interrupted. By detecting in the test coil a response signal generated by self-induction in the antenna coil of the resonant circuit and retransmitted to the test coil by inductive coupling, the response signal can be analyzed for determining whether a contactless chip card is defective. Application is well suited to the testing of antenna circuits for electronic portable devices working without contact, such as contactless chip cards, electronic labels, etc.

Abstract: The present invention relates to a method of manufacturing a MOS transistor, including the steps of delimiting, using a first resist mask N-type, drain and source implantation areas; removing the first mask and diffusing the implanted dopant; annealing, so that a thicker oxide forms above the source and drain regions than above the central gate insulation area; forming a polysilicon finger above the central gate insulation portion to form the gate of the MOS transistor; and performing a second source/drain implantation.