Abstract: A multilayer semiconductor device includes at least one structure for transmitting electrical signals, and in particular, microwave signals. The device includes at least one electrically conductive enclosure that includes a bottom plate and a top plate in two different layers. Lateral walls connect the bottom and top plates. Electrically conductive connecting strips extend into the enclosure and are in an intermediate layer, and are electrically insulated from the enclosure. The enclosure has at least one passage through which extends electrical connections of the connecting strips, which are also electrically insulated from the enclosure.

Abstract: A voltage regulator includes a regulation MOS transistor and an amplifier providing an output for driving a gate of the regulation MOS transistor. The amplifier drives the gate based upon a difference between a reference voltage and a feedback voltage. The voltage regulator may further include a circuit for making the amplifier switch to a standby mode with low current consumption when the difference between the supply voltage and the output voltage of the regulator is below a first threshold. This is done while maintaining, at the gate of the regulation transistor, a voltage that keeps the regulation transistor on. The present invention is particularly applicable to the management of power supplies in portable telephones.

Abstract: An integrated circuit capacitor includes a substrate, a first metal electrode on the substrate, and a dielectric layer on the first metal electrode. The dielectric layer includes a homogeneous combination of at least two dielectric materials having permittivities varying in an opposite way based upon an electric field, with a proportion of each dielectric material being chosen so that the integrated circuit capacitor has a desired voltage linearity. A second metal electrode is on the dielectric layer.

Abstract: A bias device includes a first branch and a second branch. The first branch includes a first bipolar device and a corresponding bias circuit. The second branch includes a second bipolar device and a corresponding bias circuit. A self-bias circuit is connected to the first and second branches. A first current generator injects a first auxiliary current into the first bipolar device. A second current generator injects a second current into the second bipolar device that is equal or proportional to the first auxiliary current. The bias device stabilizes the operating point of a circuit.

Abstract: An input circuit for memory integrated circuit cards receives a first binary signal transmitted by direct contact between the card and a reader and produces a write control signal that depends on the first binary signal to control a memory. The input circuit includes a control circuit to verify the voltage level of the first binary signal and produce a validation signal, and an inhibition circuit to inhibit the write command when the validation signal is inactive.

Abstract: An integrated circuit having as power supply voltages a low voltage reference, a logic supply voltage reference and a high voltage reference is provided. The high voltage reference is greater than the low voltage reference and the logic supply voltage reference. The integrated circuit includes an electrically programmable non-volatile memory element, and a selection and programming circuit connected thereto. A voltage control device is connected to a power supply input node of the selection and programming circuit for applying, based upon a programming control signal, the high voltage reference for programming the electrically programmable non-volatile memory element or for applying at least one logic supply voltage reference.

Abstract: A read-only memory formed of cells, each of which includes, between a selection line and a bit line, the series connection of a memory element and of a selection MOS transistor with a gate connected to a read control line. The memory elements of blank cells are P-channel MOS transistors and the memory elements of programmed cells are uniformly N-type doped semiconductor regions.

Abstract: A method is provided for fabricating a semiconductor device having a gate-all-around architecture. A substrate is produced so as to include an active central region with an active main surface surrounded by an insulating peripheral region with an insulating main surface. The active main surface and the insulating main surface are coextensive and constitute a main surface of the substrate. A fist layer of Ge or an SiGe alloy is formed on the active main surface, and a silicon layer is formed on the first layer and on the insulating main surface. The silicon layer and the first layer are masked and etched in order to form a stack on the active main surface, and the first layer is removed so that the silicon layer of the stack forms a bridge structure over the active main surface. The bridge structure defines a tunnel with a corresponding part of the active main surface.

Abstract: A system with chrominance delay lines has a first sampled channel including at least one smoothing filter, and has a second unsampled channel. A continuous bypass filter is placed in the second channel to balance the pulse response from these two channels.

Abstract: A non-volatile memory architecture with a word-based organization includes one selection transistor per word. This selection transistor is used for the selection of the word by the source of the memory cells. In this way, the selection may be done directly by the output signals from the address decoders using low voltage. The switching of a high voltage to the gates and the drains of the memory cells is done independently of this selection. This enables the required number of high voltage switches to be reduced.

Abstract: A method of illuminating a layer of a material, in particular a photosensitive resin, using a light source, in order to expose an area of that material to a useful dose of light for subsequent etching of that material in that area, consisting in effecting a first exposure through a pattern of a first mask made up of a central hole and peripheral holes with a first dose of light less than said useful dose, and a second exposure through a pattern of a second mask made up of a single hole with a second dose of light such that the cumulative total of said first dose induced through the central hole of the first mask and the second dose induced through the single hole of said second mask produces at least said useful dose over said area.

Abstract: A photodetector including an amorphous silicon photodiode having its anode connected to a reference voltage, an initialization MOS transistor connected between the cathode of the photodiode and a first supply voltage to set the cathode to the first supply voltage during an initialization phase, and means for measuring the voltage of the photodiode cathode, including saturation means for bringing the photodiode cathode to a saturation voltage close to the reference voltage immediately before the initialization phase.

Abstract: Transistor and method of manufacturing a bipolar transistor of the double-polysilicon, heterojunction-base type, in which a semiconducting layer with SiGe heterojunction is formed by non-selective epitaxy on an active region of a substrate and an insulating region surrounding the active region. At least one stop layer is formed on the semiconducting layer above a part of the active region. A layer of polysilicon and an upper insulating layer are formed on the semiconducting layer and on a part of the stop layer, leaving an emitter window free. An emitter region is formed by epitaxy in the emitter window, resting partially on the upper insulating layer and in contact with the semiconducting layer.

Abstract: A pulse-width-modulated signal is generated out of a sampled reference signal. The least significant bits of a sample of the reference signal are stored in a comparison register. At the same time, a check is made in a test circuit to find out if the sample considered corresponds to a maximum amplitude of the reference signal. If this is the case, an overflow bit is given. The overflow bit and the least significant bits of the sample considered are then linked together to obtain a comparison word. The comparison word is compared with a number given by the counter to generate the pulse-width-modulated signal.

Abstract: Each connecting pad includes a continuous top metal layer on the top metallization level and having on its top face an area for welding a connecting wire. Also, the pad has a reinforcing structure under the welding area and includes at least one discontinuous metal layer on the immediately next lower metallization level, metal vias connecting the discontinuous metal layer to the bottom surface of the top metal layer, and an isolating cover covering the discontinuous metal layer and its discontinuities as well as the inter-via spaces between the two metallic layers.

Abstract: An integrated circuit having an identification code of M bits includes a communication interface circuit for receiving a selective identification request and a selection code, and a processing circuit connected thereto. The processing circuit includes a logic comparator having a first input for receiving the selection code and a second input for receiving the identification code, and an output for delivering an equal signal if the selection and identification codes are equal. A shift register has an output coupled to the first input of the logic comparator. A serial memory stores the identification code, and has a serial output coupled to the second input of the logic comparator and to a serial input of the shift register. A controller is connected to the shift register and to the serial memory for loading the selection code into the shift register, and for applying M shift pulses to the shift register and M read pulses to the serial memory.

Abstract: An electronic circuit with digital output including an auto-stable assembly of latches (1), a control assembly (2), a blowable assembly (3), a logic gate (4) including a first input connected to a common point (14) between the auto-stable assembly (1) and the blowable assembly (3), and a second input connected to the control input (20) of the electronic circuit. A breaker (5) is controlled by the output of the logic gate (4) and arranged between the auto-stable assembly (1) and ground, and an associated process.

Abstract: A circuit for shifting at least one input switching signal includes a CMOS bistable circuit having two branches, and a circuit for accelerating the switching of the bistable circuit. The circuit for accelerating the switching allows an output transistor of each branch to be switched to the off state when an input transistor of the branch switches to the on state. The circuit for accelerating switching includes, for at least one given branch, an associated current mirror generating a turn-off current for the output transistor of the branch on the basis of a turn-on current for the input transistor of the branch.

Abstract: An FAMOS memory includes memory cells, with each memory cell including an insulated gate transistor, and a first access transistor having a drain connected to a source of the insulated gate transistor. The FAMOS memory also includes an insulation transistor having a drain and a source respectively connected to the source of the insulated gate transistors of two adjacent cells of a same row. Each insulated gate transistor has a ring structure, and a ladder-shaped separation region insulates the cells of the same row.

Abstract: In a device for reading memory cells, a precharging circuit is connected to a memory cell to be read and to a reference cell associated with the memory cell to be read. The precharging circuit precharges the output of the differential amplifier to a predetermined voltage level. The reading device further includes an inverter having a high threshold and a low threshold connected to the output of the differential amplifier. The predetermined voltage level corresponds to an intermediate level between the high and low thresholds.