Abstract: An electrically programmable memory device is proposed including: a matrix of memory cells arranged in a plurality of memory arrays and at least one redundancy array; and a substituting structure that substitutes the use of each memory array with the use of one of the at least one redundancy array in response to a failure of the memory array, wherein the memory arrays are grouped into at least one set. The substituting structure includes: a structure for associating each set with a predetermined one of the at least one redundancy array; a flag for each memory array indicative of the failure of the memory array; and a selecting for enabling each memory array or the associated redundancy array according to the corresponding flag.

Abstract: A converter is for a differential input signal into a single-ended output signal and may include a differential pair of identical first and second transistors driven by the differential input signal, and a circuit for filtering DC components, connected between the current terminal of the second transistor not in common with the first transistor of the differential pair and an output node of the converter on which the single-ended output signal is generated. The converter generates a single-ended signal without employing a transformer, in lieu thereof the converter may include a current generator biasing the differential pair by of third and fourth output transistors, in a current mirror configuration, connected in series with the first and second transistors, respectively. The converter may also include degeneration resistors of the transistors of the current mirror, dimensioned such that the gains of the converter for each of the two input nodes of the differential signal are equal and of opposite sign.

Abstract: A method for verifying an array cell of a memory device may include determining after each erase pulse or program pulse the threshold of a cell addressed through a selected array word-line and bit-line, by applying an identical voltage ramp to the selected array word-line and to the control gate of a reference cell, while biasing at a certain voltage deselected word-lines through distribution lines of the voltage generated by a charge pump generator. The method may further include temporarily decoupling the deselected word-lines from the distribution lines of the bias voltage for the duration of the voltage ramp.

Abstract: The amount of fuel to be injected in each cylinder of a multi-cylinder spark ignition internal combustion engine may be determined with enhanced precision if the fuel injection durations are determined as a function of the sensed mass air flow in all the cylinders of the engine, instead of considering only the air flow in the same cylinder. This finding has led to the realization of a more efficient approach of controlling a multi-cylinder spark ignition internal combustion engine and a feedforward control system.

Abstract: Described herein is a method for parallel generating Walsh-Hadamard (WH) channelization codes and Orthogonal Variable Spreading Factor (OVSF) channelization codes, which are channelization codes formed by a plurality of strings of antipodal digits, each having a given length L and being identifiable by respective indices I formed by strings of binary digits, each having a given length N equal to the logarithm in base two of the length L of the channelization codes, the antipodal digits of the channelization codes assuming the values +1 and ?1 and the binary digits of said indices I assuming the values 0 and 1.

Abstract: The electric charge transferred in a charge transfer phase from the pump capacitor to the tank capacitor is diminished by reducing the amplitude of the voltage swing on the transfer capacitor proportionally to the current to be supplied. This is done by limiting the maximum voltage on the pump capacitor to a certain value. This maximum value is calculated to make the voltage on the transfer capacitor reach a certain minimum voltage at the end of the charge transfer phase. A charge pump generator includes a driving circuit that isolates the pump capacitor when the voltage on it reaches the maximum value.

Abstract: A method for defining geometries in a semiconductor wafer supported on a plate electrode in a processing chamber includes forming a reusable refractory coated laminar mask. The reusable refractory coated laminar mask is formed by defining the geometries in a laminar mask substrate, forming apertures through the laminar mask substrate, and forming a layer of refractory material over at least one surface of the laminar mask substrate. The reusable refractory coated laminar mask is positioned over the semiconductor wafer. Treating of the semiconductor wafer is performed through the apertures of the reusable refractory coated laminar mask. The treating may be plasma etching or ion etching.

Abstract: In order to speed up the search for a data item in a content addressable memory and to simplify the circuit structure of the memory having associated with each row of cells a ground control line, a ground line, a match control line, and with every row of cells there is associated a search activation terminal and a match indication terminal; a method of controlling the storage and retrieval of data in the memory utilizing a unique comparison strategy for determining when the content of a comparison register is found in the memory.

Abstract: A CAM memory cell integrated on a semiconductor substrate includes a plurality of floating gate memory cells, matrix-organized in rows, called word lines, and columns, called bit lines. The cells belonging to a same row and have floating gate electrodes are short-circuited with each other in order to form a single floating gate electrode for the CAM memory cell. Advantageously, the single floating gate electrode is equipped with at least a cavity manufactured in at least a side wall of the single floating gate electrode. A process for manufacturing CAM memory cells integrated on a semiconductor substrate is also described.

Abstract: A method estimates variations of position of the rotor of a motor having a plurality of uniformly spaced sensors that generate a position pulse at every rotation by a pre-established angle of the rotor. The method may include generating a first clock signal at a first frequency, generating a second clock signal at a second frequency multiple than the first frequency by a first factor, in each interval between two consecutive position pulses, counting the number of pulses of the first clock signal comprised in the interval, counting the number of pulses of the second clock signal comprised in the interval. The method may also include that each time the number of counted pulses of the second clock reaches the number of pulses of the first clock counted in an interval that precedes the currently considered interval, signaling that the position of the rotor has varied of an angle equal to the ratio between the pre-established angle and the factor.

Abstract: A voltage regulator with a low noise discharge switch is used in non-volatile memory electronic devices, such as for discharging word lines from negative voltage potentials. The voltage regulator includes a first circuit portion with transistors for transforming a first voltage to a second voltage. The second voltage is applied to a second circuit portion with transistors. The output of the first circuit portion is coupled to ground by a discharge transistor. A third circuit portion with transistors receives a third voltage transformed, starting from the second voltage for biasing at least one word line connected downstream of the third circuit portion. A circuit portion with a discharge switch incorporates the discharge transistor, and further includes a pair of transistors connected in series to each other by an interconnection node. The interconnection node is connected to the body terminal of the discharge transistor.

Abstract: A method is provided for using a reconfigurable control structure that includes a hard-wired control unit configured to execute a pre-defined instruction set and a programmable control unit configured to execute a programmable instruction set. The method includes associating with each of a plurality of instructions to be executed an operating code to be sent to both the hard-wired control unit and the programmable control unit. The operating code includes at least one bit identifying only one of either the hard-wired control unit or the programmable control unit. The identified control unit is designed to generate control signals for the instruction to be executed.

Abstract: Low Density Parity Check encoded signals propagated over a channel are decoded by iteratively producing messages representative of the a-posteriori probability of output decoded signals as a function of check-to-bit messages produced from bit-to-check messages via check-node update computation. The check-node update computation is performed as a MIN-SUM approximation and the reliability of the output messages from the check-node update computation is determined by the least reliable incoming message M(i). The decoding includes: identifying the smallest and second smallest modulus of bit-to-check messages, the signs of output messages and the position of a least reliable incoming message, and producing an updated version of the messages representative of the a-posteriori probability as a function of the smallest or the second smallest of i-th check-to-bit messages, the signs of said output messages and the position of said least reliable incoming message.

Abstract: A process for manufacturing a non-volatile memory structure, in particular of a cross-point type provided with an array of memory cells, including forming bottom electrodes on a substrate; forming areas of active material on the bottom electrodes; and forming top electrodes on the areas of active material. The memory cells are defined at the intersection of the bottom electrode with the top electrode. At least one from among the steps of forming bottom electrodes, forming areas of active material, and forming top electrodes includes using soft-lithography techniques, chosen from amongst “microtransfer molding”, “micromolding in capillary”, and “microcontact printing”.

Abstract: A built-in self-test and self-repair structure (BISR) of memory arrays embedded in an integrated device includes at least a test block (BIST) programmable to execute on a respective memory array of the device any of a certain number of test algorithms, and a self-repair block that includes a column address generator processing the faulty address information for allocating redundant resources of the tested memory array. The BISR may further include a redundancy register on which final redundancy information is loaded at each power-on of the device and control logic for managing data transfer from external circuitry to the built-in self-test and self-repair structure (BISR) and vice versa. The BIST structure serves any number of embedded memory arrays even of different types and sizes.

Abstract: Data are transmitted over a bus including a plurality of lines, wherein energy is dissipated as a result of data transmission. Preferably, the data to be transmitted in parallel are partitioned in a plurality of clusters of data bits. Each cluster is subject to re-ordering according to a set of reordering patterns to produce a corresponding set of respective candidate clusters of data bits. Crosstalk activity values related to transmitting the various candidate clusters are calculated and compared to identify an optimum cluster of data bits that minimizes the energy dissipated as a result of transmission by jointly minimizing the switching activity and the crosstalk activity. The optimum cluster of data bits so identified is then used for transmission over the bus. The optimum cluster of data bits thus causes those bits that give rise to high crosstalk activity to be allotted to bus lines having lower crosstalk capacitance values.

Abstract: The circuit comprises a first ring oscillator comprising an odd number of inverting elements, a delay element and an output terminal; the delay element responds to a pulse at its input with a predetermined time delay with respect to a predetermined edge of the input pulse and substantially without time delay with respect to the other edge of the input pulse. With a view to avoiding start-up transients and generating pulses with a duty cycle that can be easily modified, the circuit comprises a second ring oscillator, having an output terminal connected to the output terminal of the first oscillator, and a bistable logic circuit having an output terminal connected to the common output of the first and the second oscillator. At least one of the inverting elements of the first oscillator and at least one of the inverting elements of the second oscillator form part of the bistable logic circuit.

Abstract: An interface is provided for an integrated system that includes internal circuits, with each internal circuit functioning based upon its own clock. The interface includes a finite state machine for managing asynchronous and independent interactions between the internal circuits and external circuits. The finite state machine functions based upon a unique clock and a unique reset. The interface also includes an arbitration circuit connected to the finite state machine for receiving input signals for the finite state machine. The arbitration circuit includes a memory buffer for storing signals generated by the internal circuits when the finite state machine is performing an evaluation. The interface may be used to form a command interpreter of a non-volatile memory device.

Abstract: A built-in self-test circuit for phase locked loops includes a measurement circuit for measuring outputs of the phase locked loops, and receiving as inputs a plurality of external test signals. At least one module includes a scan chain for storing the test signals for programming the phase locked loops and the measurement circuit.

Abstract: In a micro-electromechanical structure of semiconductor material, a detection structure is formed by a stator and by a rotor, which are mobile with respect to one another in presence of an external stress and are subject to thermal stress; a compensation structure of a micro-electromechanical type, subject to thermal stress and invariant with respect to the external stress, is connected to the detection structure thereby the micro-electromechanical structure supplies an output signal correlated to the external stress and compensated in temperature.