Abstract: An auxiliary interrupt control circuit is for use in a computer system including at least one peripheral for generating interrupt requests, an interrupt pending register for storing the interrupt requests, a microprocessor for processing interrupts, and an interrupt control circuit associated with the microprocessor. The auxiliary control circuit may include an auxiliary register coupled to the priority interrupt register for storing a copy of the interrupt requests. It may further include an encoder coupled to the auxiliary register and the microprocessor for generating a bit string identifying an active bit stored in the auxiliary register corresponding to a highest priority interrupt request to be processed, and for providing the bit string to the microprocessor.

Abstract: A gain stage control method may include providing a control current signal; generating a regulation current signal connected to the control current signal; transforming the regulation current signal into a biasing current, proportional to the regulation current signal; and biasing the gain stage by using the biasing current. The biasing current may be related to the control current signal by an exponential law.

Abstract: A device is provided for the correction of the power factor in forced switching power supplies. The device includes a converter, and a first control circuit coupled with the converter so as to obtain a regulated voltage on the output terminal from an alternating network input voltage. The converter includes a power transistor, and the first control circuit is suitable for driving the power transistor in every switching cycle comprising the turn-on time and the turn-off time of the power transistor. The device for the correction of the power factor further includes a second control circuit coupled to the first control circuit and capable of modulating the turn-off time of the power transistor.

Abstract: A single-loop differential switched-capacitor sigma-delta converter has a three stage double-sampling architecture with reduced current consumption. The converter is stable for large input dynamics, which makes it suitable for RF applications. The three-stage multi-bit double-sampled architecture has a single-loop architecture in which all integrators are included in a same feedback loop. This has been made possible based upon the type of integrators that are connected in cascade. Functioning of the converter is less sensitive to nonlinearities of the operational amplifiers of the integrators.

Abstract: A method for storing user data on a hard disk drive system comprises distributing user data across a plurality of independent data sectors, with each data sector including a first header having a first preamble field and a first sync mark field, and a second header having a second preamble field and a second sync mark field. The method performs a first timing recovery phase for recovering signal amplitude by acquiring phase and frequency lock from at least one of the preamble fields, and performs a subsequent frame synchronous detection phase by acquiring a corresponding sync mark field.

Abstract: A phase-locked loop includes an oscillator, a phase detector coupled to the oscillator, a charge pump coupled to the phase detector, a filter coupled to the charge pump, a voltage controlled oscillator, and a fractional frequency divider. The voltage controlled oscillator sends a VCO signal to the divider which sends an output signal to the phase detector. The divider comprises a prescaler that divides the VCO signal by an integer number and the divider emits a first signal representing the result of the division. The phase-locked loop comprises an accumulator coupled to the divider and a digital-analog converter that receives the first signal and outputs a DAC signal aligned with the first signal. The phase-locked loop comprises a circuit coupled to the digital-analog converter and to the prescaler to synchronize the DAC signal with a signal output from the prescaler.

Abstract: A feedback architecture for a PWM switching audio amplifier is, capable of compensating the effects of the demodulation filter through at least two feedback paths of the voltage applied to a load without degrading the overall loop gain of the device. Each of the feedback paths may include a respective network or filter for compensating a respective frequency pole of the cascade low-pass filter+load and establishing a certain band pass. These networks or filters may be passive networks.

Abstract: A non-volatile memory device includes addressable sectors and an ancillary volatile memory array. The ancillary volatile memory array stores protection information in the addressable sectors that is not accessible to users of the memory. The protection information is downloaded in the memory array at every power-on of the memory device. The memory array includes at least two additional columns containing preset logic information physically adjacent to the columns containing the downloaded information. A logic circuit is input with the logic information read from the additional check columns for checking the integrity of the preset logic information content of the check columns. An integrity check signal is output by the logic circuit.

Abstract: An integrated-circuit chip includes a first electrical connection are placed on an underlying layer and covered with an intermediate dielectric layer. A second electrical connection is placed on the intermediate dielectric layer and is covered with a superficial dielectric layer. External electrical connection pads are placed on the superficial dielectric layer and extend selectively over the first electrical connection. Vias pass through the superficial dielectric layer and the intermediate dielectric layer to make connection between the first electrical connection and the external electrical connection pads.

Abstract: A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A0, A1, . . . , ALS?1) to generate a first recovered string (S1), and performing a first decoding attempt using the first recovered string (S1). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S2-SN) is generated. On the basis of a comparison between the first recovered string (S1) and the second recovered string (S2-SN), a modified string (SM) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (SM).

Abstract: Data are transmitted over a bus including a plurality of lines, wherein energy is dissipated as a result of data transmission. Preferably, the data to be transmitted in parallel are partitioned in a plurality of clusters of data bits. Each cluster is subject to re-ordering according to a set of reordering patterns to produce a corresponding set of respective candidate clusters of data bits. Crosstalk activity values related to transmitting the various candidate clusters are calculated and compared to identify an optimum cluster of data bits that minimizes the energy dissipated as a result of transmission by jointly minimizing the switching activity and the crosstalk activity. The optimum cluster of data bits so identified is then used for transmission over the bus. The optimum cluster of data bits thus causes those bits that give rise to high crosstalk activity to be allotted to bus lines having lower crosstalk capacitance values.

Abstract: A micro-electro-mechanical sensor includes a microstructure having a mass which is movable with respect to a rest position, according to a predetermined degree of freedom, and a displacement-detecting device for detecting a displacement of the mass according to the predetermined degree of freedom. The displacement-detecting device includes a force feedback loop of a purely analog type, which supplies electrostatic forces tending to restore the mass to the rest position in response to a displacement of the mass according to the predetermined degree of freedom.

Abstract: Local suppression of a disturbance of a reference line is accomplished by supplying, on an internal node, a Band Gap voltage signal that is stable in temperature and power supply; driving a controlled current generator generating a controlled current signal by means of the Band Gap voltage signal; locally suppressing a disturbance of the reference line by means of a disturbance suppression circuit connected to the internal node acting on the Band Gap voltage signal; and mirroring a current signal generated on the reference line which is an output terminal of the Band Gap circuitry.

Abstract: A non-volatile memory electronic device is integrated on a semiconductor with an architecture including at least one memory matrix organized in rows or word lines and columns or bit lines of memory cells. The matrix is divided into at least a first and a second memory portions having a different access speed. The first and second memory portions may share the structures of the bit lines which correspond to one another and one by one and are electrically interrupted by controlled switches placed between the first and the second portions.

Abstract: The invention relates to an input amplifier stage, in AB class, having a controlled bias current and comprising a differential cell, inserted between a first supply voltage reference and a second voltage reference, having a differential pair of input transistors receiving respective differential signals and a pair of bias transistors, as well as an output-buffer circuit portion coupled to the cell by means of at least a supplementary parallel branch of transistors. This stage also comprises an additional circuit block, able to output the absolute value of an input current, inserted between a node of the differential cell of the input stage and a node of the supplementary branch in order to add the absolute value of a portion of the signal current to the differential cell bias current.

Abstract: Cumulative delay contributions introduced by an input buffer and by the metal line that distributes the buffered external control signal to data transfer circuits for performing a transfer of data to and from an integrated device are reduced by having the external signal distributed unbuffered through a metal line of sufficiently large size. This introduces a negligible intrinsic propagation delay being within the specified maximum admitted input pad capacitance. The delay reduction is also based on locally dedicated input buffers for each data transfer circuit, and for applying thereto a buffered replica of the external signal present on the metal line.

Abstract: A method prevents errors in execution of simultaneous read and verify operations on data being modified in two different partitions of a nonvolatile memory device. The errors are due to disturbances caused by turning on or by turning off a bank of sense amplifiers of a partition while a critical discrimination phase is being carried out by the bank of sense amplifiers of the other partition. The method includes establishing an increase in duration of one of the two operations for exceeding a minimum duration of a critical discrimination phase for the banks of sense amplifiers, and conditionally delaying conditioning of generation of a turn on or turn off signal of the bank of sense amplifiers for the partition in which the operation of an increase in duration is in progress by a predetermined time. The predetermined time is based on a command of termination, or a beginning of the critical discrimination phase by the bank of sense amplifiers of the other partition wherein the other operation is in progress.

Abstract: A single job memory device includes an array of memory cells, row and column decoders and first and second charge pump voltage regulators controlled by respective first and second control circuits that supply the row and column decoders at least during write operations of data in the array of memory cells. A third charge pump voltage generator, controlled by a third control circuit, supplies the row and column decoders during read operations of data from the array of memory cells. The memory device includes a switching circuit that, during the read operations, disconnects two of the control circuits from the respective charge pump voltage generators, transmits control signals generated by the other control circuit to the first and second charge pump voltage generators, and shorts among them the output nodes of the voltage generators on which the supply voltages of the row and column decoders are generated.

Abstract: A sensing circuit for a semiconductor memory comprising a circuit branch intended to be electrically coupled to a memory bit line having connected thereto a memory cell to be sensed. A bit line precharge circuit is provided, for precharging the memory bit line to a predetermined potential in a precharge phase of a memory cell sensing operation. An evaluation circuit is associated with the memory bit line for evaluating an electric quantity developing on the memory bit line during an evaluation phase of the memory cell sensing operation; the electric quantity that develops on the memory bit line is indicative of an information content of the memory cell. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, so that the predetermined bit line potential is reached irrespective of a memory bit line initial potential at the beginning of the precharge phase.

Abstract: The semiconductor inertial sensor is formed by a rotor element and a stator element electrostatically coupled together. The rotor element is formed by a suspended mass and by a plurality of mobile electrodes extending from the suspended mass. The stator element is formed by a plurality of fixed electrodes facing respective mobile electrodes. The suspended mass is supported by elastic suspension elements. The suspended mass has a first, larger, thickness, and the elastic suspension elements have a second thickness, smaller than the first thickness.