Abstract: A system for generating motion vectors in a motion estimator is configured for co-operating with an engine for calculating estimation error for generating motion vectors, according to estimation errors and/or motion vectors previously generated. The system comprises a program memory that contains program data for a motion-estimation algorithm, and a motion-vector memory that contains data identifying said motion vectors previously calculated.

Abstract: Described herein are a molecular memory obtained using DNA strand molecular switches and carbon nanotubes, and a manufacturing method thereof. In particular, the nonvolatile memory is manufactured according to an architecture that envisages the use of carbon nanotubes as electrical connectors and DNA strands as physical means on which to write the information. In other words, the nonvolatile memory is made by means of a set of molecular DNA strand switches, the addressing of which is controlled by molecular wires made up of carbon nanotubes.

Abstract: A manufacturing process of a stacked semiconductor device, comprising the following steps: integrating a plurality of electronic devices in a plurality of active areas realized in a semiconductor wafer; distributing an adhesive layer on active areas, splitting the semiconductor wafer into a plurality of first dies, each one comprising at least one of the active areas; mounting the plurality of first dies, which are already equipped with the adhesive layer, on a support; and mounting a plurality of second dies on the adhesive layer.

Abstract: A current sense amplifier, in particular for low voltage applications, of the type incorporated in a memory electronic device and including a differential amplifier having inputs respectively associated with a matrix circuit leg, connected to a cell to be sensed, and a reference circuit leg, connected a reference cell. At least the matrix circuit leg has a first MOS transistor to which an inverter is connected in a cascode configuration and a first input of the differential amplifier corresponding to the matrix circuit leg is coupled to a conduction terminal of the first MOS transistor and to the bitline of the memory matrix by a second MOS transistor.

Abstract: The method for programming/erasing a non volatile memory cell device includes at least one electric stress step to apply, to at least one active oxide layer of at least one memory cell of the device, a stress electric field able to remove at least a part of charges trapped in the active oxide layer. The method may be used for devices with floating gate type memory cells. The electric stress step may include the application, to one or more terminals of at least one memory cell, of potentials able to produce an electric field on a corresponding active oxide layer.

Abstract: A nonvolatile phase change memory device including a memory array formed by memory cells arranged in rows and columns, word lines connected to first terminals of memory cells arranged on the same row, and bit lines connected to second terminals of memory cells arranged on the same column; a row decoder coupled to the memory array to bias the word lines; a column decoder coupled to the memory array to bias the bit lines; and a biasing circuit coupled to the row decoder and to the column decoder to supply a first biasing voltage and a second biasing voltage to the terminals of an addressed memory cell, wherein the first biasing voltage is a positive biasing voltage and the second biasing voltage is a negative biasing voltage.

Abstract: The present invention refers to a digital apparatus suitable for driving a load. The apparatus an input for receiving a voltage signal varied by an external disturbance and comprises means for sampling at least the external disturbance such as noise, and a driving circuit such as a pulse width modulator for driving the load with a suitable output voltage. The apparatus includes a control circuit suitable for generating digital commands representative of a desired output voltage of the apparatus. The apparatus also comprises digital correction circuit suitable for generating a correction signal on the basis of the difference between the value of the current sample and the value of the previous sample of at least the external disturbance. The output of the driving circuit is governed by the correction signal.

Abstract: A method of making and testing an electronic device that includes providing first and second external pins, first and second pads on the substrate connected to the first external pin by respective bonding wires, and third and fourth pads on the substrate connected to the second external pin respective bonding wires, and to a first common line by respective resistors. With a circuit configuration of this type, the intactness of the bonding wires can easily be checked by carrying out a simple resistance measurement between the first and the second external pin.

Abstract: An arrangement is for measuring characteristic parameters of intermodulation distortion of a device under test. The arrangement may include a generator of at least two tones at different test frequencies, and an attenuation path feeding the device with a replica of the two tones attenuated of a factor equal to the gain of the device. The arrangement may also include a circuit for generating a difference signal between the signal output by the device and the two tones, and a circuit input with the difference signal and measuring the characteristic parameters as a function thereof.

Abstract: A knocking presence evaluation circuit in an internal combustion engine having a pressure sensor facing a combustion chamber for each cylinder comprised in the engine and suitable to produce a pressure signal.

Abstract: Non volatile memory cells are integrated on a semiconductor substrate, each cell comprising a floating gate electrode. These cells are made by depositing at least one protective layer on the semiconductor substrate, forming a first plurality of openings in the protective layer, etching the semiconductor substrate through the first plurality of openings so as to form a plurality of trenches, filling in the plurality of trenches and the first plurality of openings with an insulation layer, etching surface portions of the protective layer to form: surface portions of the insulation layer projecting from the semiconductor substrate divided from each other by a second plurality of openings, and lower portions of the protection layer confined below the second plurality of openings, etching the insulation layer to reduce the cross dimensions of the surface portions of the insulation layer, removing the lower portions of said protection layer until the semiconductor substrate is exposed.

Abstract: A process for manufacturing a non-volatile memory cell having at least one gate region, the process including the steps of depositing a first dielectric layer onto a semiconductor substrate; depositing a first semiconductor layer onto the first dielectric layer to form a floating gate region of the memory cell; and defining the floating gate region of the memory cell in the first semiconductor layer. The process further includes the step of depositing a second dielectric layer onto the first conductive layer, the second dielectric layer having a higher dielectric constant than 10. Also disclosed is a memory cell integrated in a semiconductor substrate and having a gate region that has a dielectric layer formed over a first conductive layer and having a dielectric constant higher than 10.

Abstract: An integrated power transistor includes emitter or source regions, and a comb-like patterned metal electrode structure interconnecting the emitter or source regions and defining at least one connection pad. The comb-like patterned metal electrode structure includes a plurality of fingers. A current sensing resistor produces a voltage drop representative of a current delivered to a load by the integrated power transistor. The current sensing resistor includes a portion of a current carrying metal track having a known resistance value and extending between one of the fingers and a connectable point along the current carrying metal track.

Abstract: A method for obtaining a high-resolution digital image from a plurality of starting images formed by pixel matrices acquired at a lower resolution includes combining the plurality of starting images to generate a provisional high-resolution image, and producing from the provisional high-resolution image a plurality of low-resolution images. Each low-resolution image corresponds to a respective starting image. At least a portion of the provisional high-resolution image is processed by modifying pixels thereof to reduce a difference between the plurality of starting images and the plurality of low-resolution images. The processing includes associating with the pixels of the provisional high-resolution image a respective uncertainty measure representing an uncertainty of the pixels, and leaving unmodified at least a subset of the pixels of the provisional high-resolution image having associated therewith a respective uncertainty measure smaller than a threshold.

Abstract: A process for manufacturing a phase change memory array, includes the steps of: forming a plurality of PCM cells, arranged in rows and columns; and forming a plurality of resistive bit lines for connecting PCM cells arranged on a same column, each resistive bit lines comprising a respective phase change material portion, covered by a respective barrier portion. After forming the resistive bit lines, electrical connection structures for the resistive bit lines are formed directly in contact with the barrier portions of the resistive bit lines.

Abstract: A system for driving columns of a liquid crystal display includes logic circuitry operating in a supply path between a first and a second supply voltage in which the first supply voltage is higher than the second supply voltage. The logic circuitry is capable of generating first logic signals and second logic signals whose value is equal to the first or second supply voltage. The system includes two level shifters coupled to the logic circuitry and operating in a supply path between a third supply voltage greater than the first supply voltage and the second supply voltage; the level shifters are capable of raising the value of the second logic signals. The system also includes a first and a second pair of transistors having different supply paths and having an output terminal in common; the first and the second pair of transistors are coupled to the level shifters to determine the drive signal of a column.

Abstract: A semiconductor memory device is provided that includes memory cells, sense amplifiers, signal lines, isolating circuits, and a precharging circuit. Each signal line is coupled to an output of at least one of the sense amplifiers and each of the isolating circuits isolates an associated signal line from the output of the corresponding sense amplifier at least during an evaluating phase of the datum stored in the memory cell. The signal lines include at least two groups of signal lines, arranged such that coupling capacitances between the lines of the first group and the lines of the second group are substantially negligible. The precharging circuit precharges the first group of signal lines to a first voltage level and the second group of signal lines to a second voltage level.

Abstract: An Integrated gyroscope includes a suspended mass; mobile actuation electrodes extending from the suspended mass; and a sensing mass connected to the actuation mass through coupling springs. The suspended mass is formed by an external part and an internal part, electrically separated by an electrical-insulation region having a closed annular shape. The electrical-insulation region is laterally completely surrounded by the external part and by the internal part. In one embodiment, the suspended mass has the shape of a closed frame delimiting an opening, the sensing mass is formed inside the opening and is connected to the internal part, and the mobile actuation electrodes are connected to the external part.

Abstract: A method of controlling a discharge of bit lines of a matrix of memory cells comprises conditioning a value of a current flowing through a bit line of the matrix during a bit line discharge phase to an absence of an indication of defectiveness of the bit line. The method allows preventing crowbar currents that otherwise flow during the bit line discharge phase when a defective bit line exhibits a short-circuit to a defective word line.

Abstract: A method for obtaining a high resolution digital image from a plurality of starting images formed by pixel matrices and acquired at a lower resolution is provided. The method may include combining the plurality of starting images to generate a provisional high resolution image formed by a pixel matrix. The method may also include associating a respective error with at least a part of the pixels of the provisional image HR(0). More particularly, this may include providing a first error associated with at least one first pixel, and at least partially processing the provisional image by modifying the pixels of this image based upon the respective errors associated therewith. A second error may also be calculated to associate with at least one second pixel situated in the vicinity of the first pixel in the matrix (HR(0)). The second error may be calculated by using the first error associated with the at least one first pixel.