Abstract: A process for manufacturing a phase change memory cell, comprising the steps of: forming a resistive element; forming a delimiting structure having an aperture over the resistive element; forming a memory portion of a phase change material in the aperture, the resistive element and the memory portion being in direct electrical contact and defining a contact area of sublithographic extension. The step of forming a memory portion further includes filling the aperture with the phase change material and removing from the delimiting structure an exceeding portion of the phase change material exceeding the aperture.

Abstract: An output buffer includes at least a first and a second stage, wherein each stage is formed by respective first transistors and second transistors coupled in series with each other between a first and a second voltage reference. The coupled first and second transistors have a common conduction terminal connected to an output terminal of the output buffer. An input terminal of the buffer is connected to control terminals of the transistors of the first stage through a first open loop driving circuit. A second feedback driving circuit is connected between the input terminal and the control terminals of the transistors of the second stage. The second feedback driving circuit includes a current detector operating to detect a maximum in the value of the current drawn by and supplied to the output buffer. A comparison block, having a threshold value, detects current in excess of the threshold value and processes information coming from the current detector to regulate an output impedance value of the output buffer.

Abstract: Described herein is a reading circuit for a nonvolatile memory device, wherein the currents flowing through an array memory cell to be read, and a reference memory cell with known contents, are converted into an array voltage and, respectively, into a reference voltage, which are compared to determine the contents of the array memory cell. The method envisages reducing the electrical stress to which the reference memory cell is subjected during reading, by generating and holding a sample of the reference voltage, then deselecting the reference memory cell, and then continuing reading using the sample of the reference voltage.

Abstract: A low noise amplifier includes a cascode device which includes at least a first and a second transistor having a terminal in common. The output terminal of the second transistor is the output terminal of the cascode device and is coupled to the output terminal of the amplifier. The amplifier includes a first circuit means suitable for the polarization of the second transistor. The first circuit means is positioned between a supply voltage and another terminal of the second transistor. The amplifier includes a second circuit means connected to the output terminal of the cascode device and is operative at a given frequency (?). The first circuit means includes a first series of a resistance and a capacitance and the second means has a second series of a resistance and a capacitance. The first series is coupled between the other terminal of the second transistor and ground and the second series is coupled between the output terminal of the cascode device and ground.

Abstract: A procedure for translating ARM instructions of a first set into instructions of a second set for execution on an LX processor comprising a core provides a first set of registers corresponding to the ARM instructions and a second set of registers corresponding to the instructions that can be executed on the LX processor. Each register of the first set is mapped in a corresponding register of the second set designed to emulate the behavior of the first register, obtaining a unique independent translation of the first set into the second set. The translation is performed by a translation device external to the LX core without altering the core, and the translation operating without accessing resources of the core, by the translating device intercepting accesses of the core to the storage area reserved to the ARM instructions.

Abstract: The method for manufacturing a micromechanical switch includes manufacturing a hanging bar, on a first semiconductor substrate, equipped at an end thereof with a contact electrode, and a frame projecting from the first semiconductor substrate. A second semiconductor substrate with conductive tracks includes a second input/output electrode and a third starting electrode, and first and second spacers electrically connected to the conductive tracks. The frame is abutted with the first spacers so that the fourth contact electrode abuts on the second input/output electrode in response to an electrical signal provided to the hanging bar by the third starting electrode.

Abstract: In a digital system using a turbo code, a method for performing iterative decoding in accordance with a Log-MAP Algorithm comprises the steps of: generating a look-up table comprising a plurality of values representative of a correcting factor; performing a first calculation to obtain a forward metric; performing a second calculation to obtain a backward metric; performing a third calculation to obtain a log-likelihood ratio for every information bit to be decoded. In accordance with the method, at least one and no more than two of such calculations are performed by the use of said look-up table for implementing the Log-MAP decoding algorithm and the remaining calculations are performed implementing a Max-Log-MAP decoding algorithm.

Abstract: To manufacture a layer of semiconductor material, a first wafer of semiconductor material is subjected to implantation to form a defect layer at a distance from a first face; the first wafer is bonded to a second wafer, by putting an insulating layer present on the second wafer in contact with the first face of the first wafer. Then, hydrogen atoms are introduced into the first wafer through a second face at an energy such as to avoid defects to be generated in the first wafer and at a temperature lower than 600° C. Thereby, the first wafer splits into a usable layer, bonded to the second wafer, and a remaining layer disposed between the defect layer and the second face of the first wafer. Prior to bonding, the first wafer is subjected to processing steps for obtaining integrated components.

Abstract: A device for power factor correction in a forced switching power supply unit is provided. The device includes a converter and a control device coupled to the converter so as to obtain from an input alternating mains voltage a direct regulated voltage on the output terminal. The converter includes a power transistor, and the control device includes an error amplifier having its inverting terminal coupled to a first signal that is proportional to the regulated voltage and its non-inverting terminal coupled to a reference voltage. A drive circuit of the power transistor is coupled to the output terminal of the error amplifier. The control device also includes a circuit for generating a current signal that is representative of the effective input voltage. The current signal is coupled to the inverting terminal of the error amplifier to vary the regulated voltage in reply to variations in the effective input voltage.

Abstract: A digital-to-analog converter (DAC) for an audio system may include at least first and second subsets of individually selectable elementary current sources for delivering analog output current contributions, a code conversion circuit for selecting elementary current sources of first and second subsets as a function of codes of a pulse code modulated (PCM) input signal. The DAC may multiply by a certain factor incoming codes of the PCM signal after their value has remained lower than a threshold for a certain period of time and for as long as their value equals or surpasses the threshold value, and may correspondingly scale and de-scale by the same factor the amplitude of the analog output current contributions produced by the elementary current sources of the two subsets.

Abstract: A method is for forming a plastic protective package for an electronic device integrated on a semiconductor and comprising an electronic circuit to be encapsulated in the protective package. The electronic device may be at least partially activated from outside of the protective package. The method may include providing a mold having a half-mold with an insert abutting towards the inside of the mold and an end having an element that can be elastically deformed to abut in pressing contact against at least one portion of the integrated circuit. The method may also include injecting a resin into the mold so that the protective package has a hole by the at least one portion of the electronic circuit.

Abstract: A micro-electro-mechanical device formed by a body of semiconductor material having a thickness and defining a mobile part and a fixed part. The mobile part is formed by a mobile platform, supporting arms extending from the mobile platform to the fixed part, and by mobile electrodes fixed to the mobile platform. The fixed part has fixed electrodes facing the mobile electrodes, a first biasing region fixed to the fixed electrodes, a second biasing region fixed to the supporting arms, and an insulation region of insulating material extending through the entire thickness of the body. The insulation region insulates electrically at least one between the first and the second biasing regions from the rest of the fixed part.

Abstract: A method for texture compressing images having a plurality of color components (R, G, B), includes decomposing the images in sub-blocks each including only one color component. At least one first predictor is defined for each sub-block and a respective set of prediction differences is computed for each sub-block. Then the prediction differences for each sub-block are sorted, and a look-up prediction differences palette is set up by defining a look-up prediction error palette. A predetermined code is associated with each column of the error palette.

Abstract: A method is provided for fabricating a semiconductor device that includes a suspended micro-system. According to the method, a silicon porous layer is formed above a silicon substrate, and the silicon porous layer is oxidized. An oxide layer is deposited, and a first polysilicon layer is deposited above the oxide layer. The first polysilicon layer, the oxide layer, and the silicon porous layer are selectively removed. A nitride layer is deposited, and a second polysilicon layer is deposited. The second polysilicon layer, the nitride layer, the first polysilicon layer, and the oxide layer are selectively removed. The silicon porous layer is removed in areas made accessible by the previous step. Also provided is a semiconductor device that includes a suspended structure fixed to at least two walls through a plurality of hinges, with the suspended structure including an oxide layer, a first polysilicon layer, a nitride layer, and a second polysilicon layer.

Abstract: A method is described for programming memory cells, in particular of the Flash type. In accordance with the method, a verification is performed with a first parallelism (M) in which a reading is carried out for determining the state of a group of memory cells, a determination is performed of a programming parallelism (np), based on the results of the verification, and a real programming of the memory cells carried out with the programming parallelism (np). An architecture is also described for programming memory cells in particular of the Flash type.

Abstract: A fuel cell is entirely fabricated on a single monocrystalline silicon substrate, and substantially overcomes leak proofing and wafer bonding difficulties and criticalities while ensuring an intrinsic sturdiness of the planarly integrated functional structure of the fuel cell. The integrated fuel cell is formed in an oxidized porous silicon region on a monocrystalline silicon substrate that is pervious to fluid flow and is electrically nonconductive with the monocrystalline silicon substrate.

Abstract: A process for manufacturing a phase change memory array includes the steps of: forming a plurality of phase change memory cells in an array region of a semiconductor wafer, the phase change memory cells arranged in rows and columns according to a row direction and to a column direction, respectively; forming a control circuit in a control region of the semiconductor wafer; forming a plurality of first bit line portions for mutually connecting phase change memory cells arranged on a same column; forming first level electrical interconnection structures; and forming second level electrical interconnection structures above the first level electrical interconnection structures. The first level electrical interconnection structures include second bit line portions laying on and in contact with the first bit line portions and projecting from the first bit line portions in the column direction for connecting the first bit line portions to the control circuit.

Abstract: A method for detecting the angular position of a rotor in a brushless electric motor, of the type in which the emission of a polarity signal of the back electromotive force by a detection circuitry associated with the motor, includes the using a bi-directional counter for counting the residence time difference of the logic states ‘0’ and ‘1’ at the output of the detection circuitry. The method is aimed at improving the detection of the instantaneous position of the rotor in a brushless motor through the detection of the zero-crossing signal.

Abstract: A geometric processing stage for a pipelined engine for processing video signals and generating processed video signal in space coordinates (S) adapted for display on a screen. The geometric processing stage includes: a model view module for generating projection coordinates of primitives of the video signals in a view space, said primitives including visible and non-visible primitives, a back face culling module arranged downstream of the model view module for at least partially eliminating the non visible primitives, a projection transform module for transforming the coordinates of the video signals from view space coordinates into normalized projection coordinates (P), and a perspective divide module for transforming the coordinates of the video signals from normalized projection (P) coordinates into screen space coordinates (S). The back face culling module is arranged downstream the projection transform module and operates on normalized projection (P) coordinates of said primitives.

Abstract: A process for the fabrication of an integrated device in a semiconductor chip envisages: forming a semiconductor layer partially suspended above a semiconductor substrate and constrained to the substrate by temporary anchorages; dividing the layer into a plurality of portions laterally separated from one another; and removing the temporary anchorages, in order to free the portions.