Abstract: A method controls performance of modem arrangements wherein a plurality of tones having associated gains with a maximum reachable value are used for carrying respective bitstreams. The method includes at least one of selectively swapping bits between the tones in the plurality and selectively changing the tone gains to optimized an error parameter. The method also includes: determining the current values for the associated gain, determining the gain margins between the maximum reachable values and the current values, and performing, to optimize the error parameter as a function of the margins, at least one of: varying the number of bits allocated to the tones, and performing a transmitted power variation by varying the gains.

Abstract: A method of calculating the discrete cosine transform (DCT) of blocks of pixels of a picture includes the steps of defining first subdivision blocks called range blocks, having a fractional and scaleable size N/2i*N/2i, where i is an integer number, with respect to a maximum pre-defined size of N*N pixels of blocks of division of the picture, referred to as domain blocks, shiftable by intervals of N/2i pixels. The method also includes the step of calculating the DCT on 2i range blocks of a subdivision of a domain block of N*N pixels of the picture, in parallel.

Abstract: A transmission system for a digital signal includes a transmitter and a receiver connected thereto by a transfer bus. The transmission system includes at least one conductive line capacitively coupled with the transfer bus.

Abstract: A common mode control circuit reduces abrupt voltage changes at the outputs of a pair of amplifiers which, in turn, reduces EMI and distortions that occur when the correlation between the signals fed to the four channels of an audio system diminishes. The common mode control circuit generates for each amplifier a reference potential that is a saturated replica of the respective differential input signal of the amplifier that saturates when the amplifier switches to a bridge configuration.

Abstract: The microreactor has a body of semiconductor material; a large area buried channel extending in the body and having walls; a coating layer of insulating material coating the walls of the channel; a diaphragm extending on top of the body and upwardly closing the channel. The diaphragm is formed by a semiconductor layer completely encircling mask portions of insulating material.

Abstract: The invention relates to an automatic decoding method for mapping and selecting a non-volatile memory device having a LPC serial communication interface in the available addressing area on motherboards. A logic structure is incorporated in the memory device, which allows a correct decoding to address the memory to the top of the addressable area or to the bottom of the same area, i.e., in both possible cases. This logic incorporates a non-volatile register whose information is stored in a Content Address Memory to enable the automatic mapping of the memory in the addressable memory area.

Abstract: A delay line for a ring oscillator circuit includes at least one delay stage having a multiple logic gate delay cells driven by a multiplexer. The multiplexer is symmetrically configured and includes multiple logic gates that are similar to the logic gates of the delay stage.

Abstract: The process for manufacturing a through insulated interconnection is performed by forming, in a body of semiconductor material, a trench extending from the front (of the body for a thickness portion thereof; filling the trench with dielectric material; thinning the body starting from the rear until the trench, so as to form an insulated region surrounded by dielectric material; and forming a conductive region extending inside said insulated region between the front and the rear of the body and having a higher conductivity than the first body. The conductive region includes a metal region extending in an opening formed inside the insulated region or of a heavily doped semiconductor region, made prior to filling of the trench.

Abstract: A method for improving the quality of a digital image acquired with a non-optimal exposure. In one embodiment, the method, which is applied directly to the image in CFA (Color Filter Array) format, identifies the regions of the image that are most important from the perceptive or contextual point of view by means of simple statistical measures. The image is then transformed by inverting the response function in such a manner as to optimize the quality of these regions.

Abstract: A content addressable memory cell for a non-volatile content addressable memory, including a non-volatile storage element for storing a content digit, a selection input for selecting the memory cell, a search input for receiving a search digit, and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage element include at least one phase-change memory element for storing in a non-volatile way the respective content digit.

Abstract: A contact structure, including a first conducting region having a first thin portion with a first sublithographic dimension in a first direction; a second conducting region having a second thin portion with a second sublithographic dimension in a second direction transverse to said first direction; the first and second thin portions being in direct electrical contact and defining a contact area having a sublithographic extension. The thin portions are obtained using deposition instead of lithography: the first thin portion is deposed on a wall of an opening in a first dielectric layer; the second thin portion is obtained by deposing a sacrificial region on vertical wall of a first delimitation layer, deposing a second delimitation layer on the free side of the sacrificial region, removing the sacrificial region to form a sublithographic opening that is used to etch a mold opening in a mold layer and filling the mold opening.

Abstract: A charge pump is proposed. The charge pump is integrated in a chip of semiconductor material and includes a plurality of capacitive elements each one connected to a corresponding circuit node of the charge pump, the circuit nodes being arranged in a sequence from an input node to an output node, a plurality of field effect transistors each one for selectively connecting a corresponding first circuit node with a second adjacent circuit node, each transistor being made in a corresponding insulated body region, and for each transistor first biasing means for equalizing the body region with the first circuit node when the transistor is closed, wherein for each transistor the charge pump further includes second biasing means for equalizing the body region with the second circuit node when the transistor is opened.

Abstract: A digital embedded architecture, includes a microcontroller and a memory device, suitable for reconfigurable computing in digital signal processing and comprising: a processor, structured to implement a Very Long Instruction Word elaboration mode by a general purpose hardwired computational logic, and an additional data elaboration channel comprising a reconfigurable function unit based on a pipelined array of configurable look-up table based cells controlled by a special purpose control unit, thus easing the elaboration of critical kernels algorithms.

Abstract: A trimming structure for trimming functional parameters of an Integrated Circuit—IC—(100) includes a first (115a) and at least one second functional blocks (115b, . . . ,115n) with which a first (Vrg,a) and at least one second IC functional parameters (Vrg,b, . . . ,Vrg,n) are respectively associated. The trimming structure includes respective trimmable circuit structures (205a,210a, . . . ,205n,210n) included in the first and at least one second functional blocks, and trimming configuration storage (110) for storing trimming configurations for the trimmable circuit structures. A change in the trimming configuration of the first functional block causes a corresponding change in the trimming configuration of the second functional block.

Abstract: A method is provided for contact opening definition for active element electrical connections. According to the method, a layer of BPSG is formed on a surface of an integrated circuit, and a transparent layer of nitride UV is formed above the layer of BPSG. Preferably, the transparent layer of nitride UV is formed by deposition using an HDP process and has a thickness of less than about 500 ?. In one embodiment, after forming a transparent layer of nitride UV, two overlapped layers of BARC and resist are formed on the surface of the integrated circuit. Also provided is a machine-readable medium encoded with a program for contact opening definition for active element electrical connections.

Abstract: A memory system comprising a semiconductor memory for storing digital data, said memory being connectable to a control device in order to receive an address signal and to make data selected through the output-available address signal. The system is characterised in that it comprises a generating circuit for activating a wait signal to be forwarded to the control device during reading operations in such a way as to indicate the non-availability of the data to be read. The generating circuit is such to deactivate the wait signal, in such a way as to indicate the availability of the data to be read, following a waiting time interval correlated with an effective access time for said memory.

Abstract: A method regulates the time constant matching of a DC/DC converter phase, further to a variation of a load applied to an output of said phase. Such phase being associated with a coil network, with a series RL circuit and a reading network 10, with a series RC circuit connected in parallel to the coil network. The method includes an acquisition step, suitable to acquire the trend of a voltage detected across the capacitance CD of the reading network 10, transforming it into a current trend, a detection step suitable to identify a variation above a certain threshold value of said current trend, an identification step, enabled by said detection step, suitable to determine a slope of said current trend and a regulation step suitable to adapt the value of said resistance RD based on said slope determined by said identification step.

Abstract: A process for manufacturing a non-volatile memory cell including a floating gate MOS transistor, including the steps of: forming a gate dielectric over a surface of a semiconductor material layer; forming a conductive floating gate electrode insulated from the semiconductor material layer by the gate dielectric; forming at least one isolation region laterally to the floating gate electrode; excavating the at least one isolation region; filling the excavated isolation region with a conductive material; and forming a conductive control gate electrode of the floating gate MOS transistor insulatively over the floating gate, wherein the step of forming the floating gate electrode includes: laterally aligning the floating gate electrode to the at least one isolation region; and the step of excavating includes: lowering an isolation region exposed surface below a floating gate electrode exposed surface, the lowering exposing walls of the floating gate electrode; forming a protective layer on exposed walls of the flo

Abstract: In order to manage, in the interrupt stage, a memory stack associated with a microcontroller according to a Program Counter signal and to a Condition Code Register signal that can be contained in respective registers, a first part of memory stack is provided which comprises a register for the Program Counter signal, and a second part of memory stack consisting of a bank of memory elements equal in number to the number of bits of the Condition Code Register signal for the number of the interrupts of the microcontroller. The two parts of stack are made to function in parallel by respective stack-pointer signals.

Abstract: A driving network for an emitter-switching circuit comprises a pair of cascode-configured transistors, the one of the bipolar type and the other of the MOS type, and the driving network is of the type comprising a driving block for respective conduction terminals and of said pair of transistors. The driving network (20, 30) further comprises sensor means in the driving block suitable for measuring a voltage to be compared with a reference value in a first comparator block. A negative feedback network between the output of the comparator and the driving block to provides a voltage value to said driving block to bias the conduction terminal of the bipolar transistor of the emitter-switching circuit in order to regulate the storage time thereof.