Abstract: A non volatile memory device is integrated on a semiconductor substrate and includes a matrix of memory cells with an associated circuitry. The process for forming the memory device includes forming in the semiconductor substrate first dielectric insulation regions of the matrix to define and insulate first active areas of the matrix from each other, and forming in the semiconductor substrate second dielectric insulation regions of the associated circuitry to define and insulate second active areas of the circuitry from each other. At least one dielectric layer is formed on the first and second active areas. A first conductive layer is deposited on the whole device, and floating gate electrodes of the memory cells of the matrix are defined in the first conductive layer, with the first conductive layer being removed from the associated circuitry.

Abstract: A memory device comprises a plurality of banks of storage locations accessible in response to access requests. Data refresh means are provided for refreshing data stored in the storage locations within prescribed times, whereby the memory device autonomously perform a refresh. A cache memory is embedded in the memory device. The cache memory has a plurality of cache storage locations for storing data contained in recently accessed storage locations. Access control means control the access to the storage locations and to the cache storage locations in response to the access requests: an access request is diverted to the cache memory whenever access to anyone of the recently accessed storage locations is requested. Any cache storage location is freely associable to any storage location in any bank, the association between any cache storage location and a storage location in the plurality of banks being established by a storage location association table in the access control means.

Abstract: A method for sensing a back electromotive force induced in a winding of a voice coil electro-mechanical actuator controlled in a discontinuous mode by alternating conduction phases to off-phases includes sensing voltage at terminals of the winding during an off-phase The winding is driven during a conduction phase immediately preceding the off-phase to invert, during a final portion of the conduction phase before entering an off-phase, a direction of flow of the current through the winding.

Abstract: A method for manufacturing insulating structures in a semiconductor substrate includes forming a first insulating layer on the semiconductor substrate, forming a stop layer on the first insulating layer, and forming a barrier layer on the stop layer. The barrier layer is selective with respect to the stop layer. A screen layer is formed on the barrier layer. A portion of the screen layer is selectively removed for forming an opening therethrough for exposing a portion of the barrier layer. The exposed barrier layer is removed for exposing a portion of the stop layer. The exposed stop layer is removed for exposing a portion of the semiconductor substrate. The method further includes removing the remaining barrier layer, and removing a portion of the exposed semiconductor substrate for forming a trench therein.

Abstract: A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a plurality of emitter regions of P type formed in the base regions; and a plurality of base contact regions of N type and a higher doping level than the base regions, formed in the base regions, wherein each base region is shared by at least two adjacent bipolar transistors.

Abstract: A circuit for selectively converting at least one analog signal into corresponding digital codes. The circuit includes a management block having a plurality of inputs, each adapted for receiving a respective request signal carrying a request to convert the at least one analog signal. The management block is adapted to assign a priority level to the request signals based upon the input where the request signals are received, and is further operative to select one of the request signals based upon the assigned priority level and output a conversion start-up signal corresponding to the selected request signal. The circuit has a conversion block for receiving east one analog signal input and is connected to the management block to receive the conversion start-up signal as input, and start up conversion of the at least one analog signal.

Abstract: A built-in self-test circuit adapted to be embedded in an integrated circuit for testing the integrated circuit, including in particular a collection of addressable elements, for example a semiconductor memory. The BIST circuit comprises a general-purpose data processor programmable for executing a test program for testing the integrated circuit. The BIST circuit comprises an accelerator circuit cooperating with the general-purpose data processor for autonomously conducting operations on the integrated circuit according to the test program. The accelerator circuit comprises configuration means adapted to be loaded with configuration parameters for adapting the accelerator circuit to the specific type of integrated circuit and the specific type of test program.

Abstract: A power device is formed by a thyristor and by a MOSFET transistors, series-connected between a first and a second current-conduction terminal. The power device moreover has a control terminal connected to an insulated-gate electrode of the MOSFET transistor and receiving a control voltage for turning on/off the device, and a third current-conduction terminal connected to the thyristor for fast extraction of charges during turning-off. Thereby, upon turning off, there are no current tails, and turning off is very fast. The power device does not have parasitic components and consequently has a very high reverse-bias safe-operating area.

Abstract: To correct for harmonic distortion of a power bridge, the form of a pulse at the output of the power bridge and of estimate of non idealities under different current conditions is acquired. An estimate of a current at the output of the power bridge is also acquired. The switching control signal applied to the power bridge is then regulated based on the acquired estimates. More specifically, an area error introduced by the estimated non-idealities of the power bridge for a certain output current is determined and the edges of the switching control signal input to the power bridge are temporally shifted in response to the determined area error so as to account for the determined area error and correct for harmonic distortion concerns in the output signal.

Abstract: A hardware device is for performing crossover and mutation operations based upon a genetic algorithm. The hardware device may include a random or pseudo-random number generator, and a crossover block, conditioned with a random crossover index, for generating output crossover bit-strings from current bit-strings. The device may also include a mutation block, conditioned with a random mutation index, for generating output bit-strings by switching at least one bit of each input bit-string pointed to by the mutation index. A memory may temporarily store the current bit-strings and the output bit-strings. In addition, the hardware device may include a control unit, interfaced with the random number generator, the crossover block, the mutation block and the memory and managing their functioning by generating respective control signals therefor.

Abstract: A micromachined device made of semiconductor material is formed by: a semiconductor body; an intermediate layer set on top of the semiconductor body; and a substrate, set on top of the intermediate layer. A cavity extends in the intermediate layer and is delimited laterally by bottom fixed regions, at the top by the substrate, and at the bottom by the semiconductor body. The bottom fixed regions form fixed electrodes, which extend in the intermediate layer towards the inside of the cavity. An oscillating element is formed in the substrate above the cavity and is separated from top fixed regions through trenches, which extend throughout the thickness of the substrate. The oscillating element is formed by an oscillating platform set above the cavity, and by mobile electrodes, which extend towards the top fixed regions in a staggered way with respect to the fixed electrodes. The fixed electrodes and mobile electrodes are thus comb-fingered in plan view but formed on different levels.

Abstract: A method for designing a new prunable S-random interleaver class to be used as a constituent part of turbo codes. With respect to previously proposed solutions the method has the advantage of being prunable to different block sizes while exhibiting at the same time, for any considered block size, performance comparable with the optimized “ad hoc” S-random interleavers. Another advantage is that, as for every S-random interleaver, the design rules are independent of the constituent codes and of the puncturing rate applied to the turbo code. Therefore, these interleavers potentially can find applications in any turbo code scheme that requires interleaver size flexibility and code rate versatility, thanks to the advantage of requiring a single law storage (i e., one ROM storage instead of several ROMs) from which all the others are obtained by pruning, without compromising the overall error rate performance.

Abstract: A switch block for FPGA architectures combining hardware and software techniques in order to reduce both active and standby leakage power.

Abstract: A system-on-chip arrangement having, in possible combination with a processor, a plurality of reconfigurable gate array devices, and a configurable Network-on-Chip connecting the gate array devices to render the arrangement scalable. The arrangement lends itself to be operated by mapping in one device of the gate array a set of processing modules, and configuring another device of the plurality of gate array devices as a microcontroller having stored therein software code portions for controlling inter-operation of the processing modules stored in the one device of the plurality. The arrangement is thus adapted, e.g., to handle different computational granularity levels.

Abstract: A circuit for computing the inner of scalar product of two vectors in a finite Galois field defined by a generator polynomial, wherein each vector includes at least two elements belonging to said finite field, comprises one or more look-up tables storing digital words indicative of said possible combinations and said possible reductions. The digital words in question are defined as a function of the second elements of said vectors and the generator polynomial of the field. The input register(s) and the look-up table(s) are configured to co-operate in a plurality of subsequent steps to generate at each step a partial product result identified by at least one of digital word addressed in a corresponding look-up table as a function of the digital signals stored in the input register(s). The circuit also includes an accumulator unit for adding up the partial results generated at each step to give a final product result deriving from accumulation of said partial results.

Abstract: A control circuit for an inductive load driver includes a control block activated by a trigger signal and an output coupled to the control terminal of a power element. The control circuit includes an auxiliary current generator capable of delivering a current that is added to the current provided by control block and the sum of these currents is provided to the control terminal of the power element. The auxiliary current generator enables the inductive load driver to operate normally even though the trigger voltage is less than an optimal voltage value.

Abstract: A semiconductor power device includes an insulated gate and a trench-gate structure. The trench-gate structure is formed on a semiconductor substrate covered by an epitaxial layer. The trench is formed in the semiconductor to form the device gate region. A dielectric coating is provided on the inner and bottom walls of the trench. The gate region includes a conductive spacer layer on the coating layer only on the inner walls of the trench.

Abstract: In a body of semiconductor material, a field region separates a first active area and a second active area. A drain region is formed in the first active area; a body region is formed in the second active area and accommodates a source region. A body-contact region is formed inside the source region and extends from the surface as far as the body region. An insulating layer extends on top of the surface and accommodates a plurality of metal contacts, which extend as far as the drain region, the source region and the body-contact region. The body-contact region is self-aligned to a respective contact.

Abstract: A method of compressing digital images acquired in CFA format that utilizes optimized quantization matrices. The method, basing itself on the statistical characterization of the error introduced during the processing phase that precedes compression, appropriately modifies the coefficients of any initial quantization matrix, even of a standard type, obtaining a greater compression efficiency without introducing further quality losses.

Abstract: A microprocessor system includes a high speed primary bus, a plurality of master devices coupled to the high speed primary bus, and a plurality of peripherals coupled to the high speed primary bus. The peripherals include at least one memory. An arbiter circuit is coupled to the high speed primary bus for managing access requests to the high speed primary bus by any one of the master devices. The microprocessor system further includes a secondary bus, and a bridge interface circuit coupled between the high speed primary bus and the secondary bus. The bridge interface circuit includes a direct memory access controller so that during each data transfer routine between a peripheral connected to the secondary bus and one of the peripherals reduces to a single transfer phase engagement of the high speed primary bus.