Abstract: An integrated electronic circuit includes a plurality of active circuits connected together in cascade. A feedback loop is between an output of a last active circuit and an input of a first active circuit so that the plurality of active devices function as a non-linear device, such as a capacitor. The integrated electronic circuit may be integrated or used in association with a circuit network including other non-linear devices.

Abstract: A driving circuit for piezoelectric actuators comprises a chip of semiconductor material integrating both an interface circuit receiving at input a control signal generated by a control logic unit, and a power circuit driving the piezoelectric actuators. The power circuit is directly connected to the output of the interface circuit.

Abstract: A random access memory (RAM) includes at least two memory banks. Each memory bank includes an array of dynamic random access memory (DRAM) cells, and self-refresh circuits for continuously submitting the DRAM cells to a refresh operation independent of the other memory banks. A first circuit selectively accesses one of the memory banks in response to an external access request. A second circuit suspends the refresh operation in the accessed memory bank while processing the external access request, and while the refresh operations in non-selected memory banks are not suspended.

Abstract: A Common Rail injection system of an endothermic engine, the injection system including at least one fuel pressure accumulating tank, of the rail type, having an input in fluid communication with a high-pressure pump and a plurality of outputs for feeding corresponding injectors by using pressure regulating means connected and depending on an electronic control unit. Advantageously a virtual pressure sensor includes a fluid-dynamic model of the accumulating tank suitable to estimate and to obtain fluid pressure values used by the electronic control unit for driving the injection means of the Common Rail injection system.

Abstract: The method for manufacturing a micromechanical switch includes manufacturing a hanging bar, on a first semiconductor substrate, equipped at an end thereof with a contact electrode, and a frame projecting from the first semiconductor substrate. A second semiconductor substrate with conductive tracks includes a second input/output electrode and a third starting electrode, and first and second spacers electrically connected to the conductive tracks. The frame is abutted with the first spacers so that the fourth contact electrode abuts on the second input/output electrode in response to an electrical signal provided to the hanging bar by the third starting electrode.

Abstract: A method and a circuit for minimizing glitches in phase-locked loops is presented. The circuit includes an input terminal connected to an input of a phase detector; a series of a charge pump generator, a filter and a voltage controlled oscillator connected downstream of the phase detector; and a frequency divider feedback connected between an output of the voltage controlled oscillator and a second input of the phase detector. The circuit provides for the inclusion of a compensation circuit connected between the charge pump generator and the filter to absorb an amount of the charge passed therethrough. This compensation circuit includes a storage element connected in series to two switches. The first switch is coupled to and controlled by an output of the charge pump and the second switch is coupled to and controlled by an output of a phase detector.

Abstract: This invention relates to a memory cell which comprises a capacitor having a first electrode and a second electrode separated by a dielectric layer. Such dielectric layer comprises a layer of a semi-insulating material which is fully enveloped by an insulating material and in which an electric charge is permanently present or trapped therein. Such electric charge accumulated close to the first or to the second electrode, depending on the electric field between the electrodes, thereby defining different logic levels.

Abstract: A process for forming a thin layer of Silicon nanocrystals in an oxide layer is disclosed. The process includes, on a semiconductive substrate, thermally oxidizing a first portion of the substrate into an oxide layer, forming Silicon ions within the layer of oxide, and thermally treating the Silicon ions to become the thin layer of Silicon nanocrystals. In the inventive process the formation of the Silicon ions is by ionic implantation of the Silicon ions into the oxide at an ionization energy of between 0.1 keV and 7 keV, and preferably between 1 and 5 keV. This allows the Silicon atoms to coalesce in a lower temperature than would otherwise be possible. Additionally, more than one layer of nanocrystals can be formed by performing more than one implantation at more than one energy level. Embodiments of the invention can be used to form non-volatile memory devices with a very high quality having a very small size.

Abstract: A circuit for regulating an output voltage of a charge pump includes a regulator connected to an output of the charge pump. The regulator includes a voltage divider for dividing the output voltage. A filter has a first input for receiving the divided output voltage, a second input for receiving a control signal, and an output for providing a filtered divided output voltage. A comparator has a first input for receiving the divided output voltage, a second input for receiving a reference voltage, a third input for receiving the filtered divided output voltage, and an output for providing a digital signal based upon a comparison of the divided output signal, the reference voltage and the filtered divided output voltage. A logic control circuit has a first input for receiving a clock signal, a second input for receiving the digital signal from the comparator, and an output for providing a timing signal.

Abstract: Binary words are converted between a non-encoded format and a compressed encoded format, in which the binary words are, at least in part, represented by encoded bit sequences that are shorter than the respective binary word in the non-encoded format. The shortest encoded bit sequences are selected according to the statistical recurrence of the respective words in the non-encoded format, and associated with the binary words with higher recurrence are encoded bit sequences comprising bit numbers that are accordingly smaller. The correspondence between binary words in non-encoded format and the encoded bit sequences associated to them is established by means of indices of an encoding vocabulary. The conversion process includes: arranging the indices in an ordered sequence; organizing the sequence into groups of vectors; splitting each group into a given number of vectors; and encoding the vectors independently from one another.

Abstract: A method of image analysis applicable to the analysis of arrays, such as DNA or protein microarrays. In the method the luminous spots of the array are filtered and isolated without any intervention of the operator by using a technique of morphological filtering. The spots thus isolated are subsequently analyzed by a fuzzy logic algorithm.

Abstract: A method of fabricating a MOS transistor with a controllable and modulatable conduction path through a dielectric gate oxide is disclosed, wherein the transistor structure comprises a dielectric oxide layer formed between two silicon plates, and wherein the silicon plates overhang the oxide layer all around to define an undercut having a substantially rectangular cross-sectional shape. The method comprises the steps of: chemically altering the surfaces of the silicon plates to have different functional groups provided in the undercut from those in the remainder of the surfaces; and selectively reacting the functional groups provided in the undercut with an organic molecule having a reversibly reducible center and a molecular length substantially equal to the width of the undercut, thereby to establish a covalent bond to each end of the organic molecule.

Abstract: An RGB digital video signal destined to be displayed on a display such as a liquid crystal display (LCD) is converted from the RGB color space to the YUV color space. The signal converted into the YUV color space is subjected to at least a processing operation selected among a sub-sampling operation (24) and a data compression operation (26). The signal is then stored in a memory and the signal read from said memory (12) is then subjected to at least a return operation (28, 30) complementary to the aforesaid processing operation (24, 26). The signal subjected to the aforesaid return operation is lastly reconverted from the YUV color space to the RGB color space, thus being susceptible to be displayed on the display.

Abstract: The invention relates to a circuit device for realizing a non-linear reactive elements scale network, wherein the non-linear elements of the network are pairs of inductive and capacitive components cascade connected between a pair of input terminals and a pair of output terminals. Advantageously in the invention, each component of the network is formed by cascade connecting a first and a second transconductance integrator with each other.

Abstract: A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a plurality of emitter regions of P type formed in the base regions; and a plurality of base contact regions of N type and a higher doping level than the base regions, formed in the base regions, wherein each base region is shared by at least two adjacent bipolar transistors.

Abstract: A switching voltage regulator adapted for providing a regulated voltage at an output terminal is described which comprises at least one MOS transistor having a non-drivable terminal coupled with said output terminal and a control circuit receiving a signal that is representative of the current signal flowing in said MOS transistor. The control circuit comprises a compensation device adapted for cancelling the thermal variation of said signal that is representative of the current signal flowing in said MOS transistor.

Abstract: An improved Finite Impulse Response (FIR) filter is presented which provides linear scalability and implementation without the need for delay lines. A multiprocessor architecture includes a plurality of ALUs (Arithmetic and Logic Unit), Multipliers units, Data cache, and Load/Store units sharing a common Instruction cache. A multi-port memory is also included. An assigning functionality assigns to each available processing unit the computation of specified unique partial product terms and the accumulation of each computed partial product on specified output sample values.

Abstract: A method is described for manufacturing electronic semiconductor devices comprising the steps of depositing in sequence a layer of hydrophobic material and a “deep UV” photo-resist layer on a semiconductor substrate, selectively removing the “deep UV” photo-resist layer and hydrophobic material in order to expose definite portions of the semiconductor substrate and etch the exposed portions by means of an watery acid solution. This method allows semiconductor devices to be manufactured, also having very critical sizes and with a convenient resolution and control of circuit patterns formed thereon through etching with watery acid solutions.

Abstract: Digital signals are transmitted on a bus at given instants selectively in a non-encoded format and an encoded format. The decision whether to transmit the signals in non-encoded format or in encoded format is taken in part, based on a comparison of the signal to be transmitted on the bus for an instant of the aforesaid given instants with the signal transmitter on the bus for the preceding instant, so as to minimize switching activity on the bus.

Abstract: A method for generating cryptographically secure (or unpredictable) pseudo-random numbers uses simple functions whose inverse is not a well-defined function and has a large number of branches, although the inverse could be easily computed on each particular branch. In this way the sequence of numbers is practically unpredictable and at the same time may be generated using very simple functions.