Abstract: A microprocessor system includes a high speed primary bus, a plurality of master devices coupled to the high speed primary bus, and a plurality of peripherals coupled to the high speed primary bus. The peripherals include at least one memory. An arbiter circuit is coupled to the high speed primary bus for managing access requests to the high speed primary bus by any one of the master devices. The microprocessor system further includes a secondary bus, and a bridge interface circuit coupled between the high speed primary bus and the secondary bus. The bridge interface circuit includes a direct memory access controller so that during each data transfer routine between a peripheral connected to the secondary bus and one of the peripherals reduces to a single transfer phase engagement of the high speed primary bus.

Abstract: An optimised architecture to implement connections between logic blocks and routing lines in reconfigurable gate arrays including connection blocks to connect inputs and outputs of different logic elements by means of connection wires, each connection block including a single line of pass transistor switches; and a decoding stage to drive the pass transistor switch.

Abstract: A fractional-type phase-locked loop circuit is proposed for synthesising an output signal multiplying a frequency of a reference signal by a fractional conversion factor, the circuit including means for generating a modulation value, means for generating a feedback signal dividing the frequency of the output signal by a dividing ratio, the dividing ratio being modulated according to the modulation value for providing the conversion factor on the average, means for generating a control signal indicative of a phase difference between the reference signal and the feedback signal, means for controlling the frequency of the output signal according to the control signal, and means for compensating a phase error caused by the modulation of the dividing ratio; in the circuit of an embodiment of the invention, the means for compensating includes means for calculating an incremental value, indicative of an incremental phase error, according to the conversion factor and the modulation value, means for calculating a corr

Abstract: The present invention relates to method to improve RF measurements accuracy on an automatic testing equipment (ATE) for IC wafers by implementing a test board de-embedding phase, wherein each wafer includes a device under test located on a wafer die plane and being contacted by probecard needles of a probecard that is coupled to a configuration board through a probe interface board (PIB), the method including the following phases: performing an automatic calibration phase of the testing equipment up to an internal plane located inside the automatic testing equipment; performing a calibration plane transfer up to a plane of the configuration board using a predetermined number of calibration standard loads realized on the wafer; performing a test boards de-embedding phase up to the wafer die plane.

Abstract: A charge pump circuit, connected between a first voltage reference and an output terminal, comprises at least two parallel-coupled stages having an elementary charge pump circuit connected between said first voltage reference and said output terminal, and adjustment circuitry connected between said output terminal and respective control terminals of said at least two stages. This adjustment circuitry is arranged to select for actuation an appropriate combination of these elementary stages according to the current absorbed from a load connected to the output terminal.

Abstract: A method for automatically calibrating a phase locked loop (PLL) system includes estimating a frequency value of an input signal applied to the system. Based on the estimated frequency value, a driving signal is generated for a plurality of internal switches in the PLL system. A PLL system may also implement this automatic calibration method.

Abstract: A semiconductor electronic device includes a die of semiconductor material and a support. The die of semiconductor material includes an integrated electronic circuit and a plurality of contact pads associated with the electronic circuit and connected electrically to the support by wire leads. Each contact pad may include a lower layer of aluminum, copper, or alloys thereof, and an upper layer including at least one film of a metal and/or metallic alloy including nickel, palladium, or alloys thereof, and being deposited by an electroless chemical process.

Abstract: An integrated circuit including a vertical power component having a terminal formed by a chip substrate of a first conductivity type, a control circuit thereof, the control circuit isolated from the substrate by an isolation region of a second conductivity type, and a protection structure against polarity inversion of a substrate potential. The protection structure includes a first bipolar transistor with an emitter connected to said isolation region and a collector connected to a reference potential input of the integrated circuit, a bias circuit for biasing the first bipolar transistor in a reverse saturated mode when the substrate potential is higher than the reference potential, and a second bipolar transistor with an emitter connected to the substrate and a base coupled to the isolation region for coupling the isolation region to the substrate through a high-impedance when the substrate potential is lower than the reference potential.

Abstract: A resistive structure integrated on a semiconductive substrate is described. The resistive structure has a first type of conductivity formed into a serpentine region of conductivity which is opposite to that of the semiconductive substrate. In at least two parallel portions of the serpentine region, there is at least one trench filled with an insulating material.

Abstract: The phase-change nonvolatile memory array is formed by a plurality of memory cells extending in a first and in a second direction orthogonal to each other. A plurality of column-selection lines extend parallel to the first direction. A plurality of word-selection lines extend parallel to the second direction. Each memory cell includes a PCM storage element and a selection transistor. A first terminal of the selection transistor is connected to a first terminal of the PCM storage element, and the control terminal of the selection transistor is connected to a respective word-selection line. A second terminal of the PCM storage element is connected to a respective column-selection line, and a second terminal of the selection transistor is connected to a reference-potential region while reading and programming the memory cells.

Abstract: According to the multilevel programming method, each memory location can be programmed at a non-binary number of levels. The bits to be stored in the two locations are divided into two sets, wherein the first set defines a number of levels higher than the non-binary number of levels. During programming, if the first set of bits to be written corresponds to a number smaller than the non-binary number of levels, the first set of bits is written in the first location and the second set of bits is written in the second location; if it is greater than the non-binary number of levels, the first set of bits is written in the second location and the second set of bits is written in the first location. The bits of the first set in the second location are stored in different levels with respect to the bits of the second set.

Abstract: An integrated device comprises a first conductive region and a first insulating region of dielectric material covering the first conductive region. A first through region of electrically conductive material extends inside the first insulating region, and is in direct electrical contact with the first conductive region. A second conductive region, arranged above the first insulating region, is in a position not aligned and not in contact with the first through region. A second insulating region of dielectric material covers the second conductive region. A second through region of electrically conductive material extends inside the second insulating region as far as the first through region and is aligned and in direct electrical contact with the first through region. A third conductive region, arranged above the second insulating region, is aligned and in direct electrical contact with the second through region.

Abstract: Described herein is a method for transmitting data on a bus with minimization of the bus switching activity, comprising the steps of converting the datum to be transmitted from its own original format to a transmission format that minimizes the switching activity on the bus, said conversion consisting in swapping the position of one or more bits of the datum to be transmitted, the swapping being performable according to a plurality of different variants, each of which is identified by a respective sorting pattern, and selecting, between the various sorting patterns, an optimal sorting pattern that minimizes the bus switching activity upon transmission on the bus of the datum generated using said optimal sorting pattern.

Abstract: An analog-to-digital converter (200) with a pipeline architecture for converting an analog input signal into a digital output signal with a predefined resolution is proposed. The converter includes a plurality of stages (1053-1050) each one having means (110, 115) for converting an analog local signal into a digital local signal with a local resolution lower than said resolution, means (120, 125) for determining an analog residue indicative of a quantization error of the means for converting, and means (130) for amplifying the analog residue by an inter-stage gain corresponding to the local resolution to generate the analog local signal for a next stage, and further includes means (204) for combining the digital local signals of all the stages into the digital output signal weighting each digital local signal according to a digital weight depending on the corresponding inter-stage gain.

Abstract: Matrix of memory cells formed using a method allowing for a self-alignment of the respective source region with the respective field oxide layer and the respective overlying polysilicon layer of each single cell of the matrix, the matrix including at least one first ROM memory cell suitable for permanently storing a first logic level, associated with a respective row and a respective column of the matrix, the first cell including a silicon substrate of a first conductivity type over which a first isolation region and a second isolation region are formed delimiting therebetween a longitudinal stripe, a gate element extending transversally through the stripe from at least one side of the first isolation region to at least one side of the second isolation region, a third region of a second conductivity type and a fourth region of a second conductivity type formed in the substrate along the stripe, and a field oxide region adapted to prevent the formation of a conductive channel in the substrate, and at least a s

Abstract: The method of a protection circuit includes a reference voltage source and at least one circuit which are connected together via a switch. A memory element is connected to the input of the circuit, downstream of the switch. The switch is temporarily opened by a control signal generated by a monostable circuit when detecting switching of power elements belonging to an electronic device embedding the protection circuit. When the switch is open, the memory element supplies the circuit with the reference voltage previously stored. In this way, switching of the power element that might cause noise on the reference voltage cannot disturb the circuit and thereby cannot cause a faulty operation of the latter.

Abstract: A device for detecting load impedance having an analog circuit portion for detecting the impedance value of a load, and a digital circuit portion adapted to provide load impedance type information. The analog circuit portion having two power MOS transistors connected in series to each other and between a supply voltage and the ground, and a pair of mirror MOS transistors common-connected with their respective gate terminals to the gate terminals of the power MOS transistors. The digital circuit portion includes a first comparitor to determine whether the output current of an audio amplifier is higher or lower than a threshold value and a second comparator to determine whether the output voltage of the amplifier is higher than a threshold voltage, a memory to store output signals of the first and second comparitors, and a logic circuit arranged in cascade with the memory to output a load-type indication signal.

Abstract: An exponentially variable gain mixer circuit includes an oscillating circuit generating an alternating differential signal. A correction circuit is connected to the oscillating circuit and includes a first amplifier and a differential amplifier. The first amplifier receives an external gain variation command and generates a differential output signal that includes a control voltage and a bias voltage. The differential amplifier receives the alternating differential signal and generates a differential modulation signal. A variable gain mixer receives an input differential signal and generates an amplified differential signal as a function of the differential modulation signal and the control voltage.

Abstract: A method of manufacturing a non-volatile memory device includes depositing a first layer on a semiconductor substrate, and a portion of the first layer is selectively removed to form a memory array area. A second layer is deposited on the memory array area and on adjacent areas of the semiconductor substrate contacting the memory array area. The second layer has a thickness that is substantially equal over the memory array area and over the adjacent areas. The method further includes forming a screening layer on the second layer on the adjacent areas except for outer peripheral portions thereof adjacent the memory array area. The thickness of the second layer exposed on the memory array area and on the outer peripheral portions of the adjacent areas is reduced so that a resulting thickness is less than a thickness of the first layer.

Abstract: A method is for forming a plastic protective package for an electronic device integrated on a semiconductor and comprising an electronic circuit to be encapsulated in the protective package. The electronic device may be at least partially activated from outside of the protective package. The method may include providing a mold having a half-mold with an insert abutting towards the inside of the mold and an end having an element that can be elastically deformed to abut in pressing contact against at least one portion of the integrated circuit. The method may also include injecting a resin into the mold so that the protective package has a hole by the at least one portion of the electronic circuit.