Abstract: A method for generating interrupt commands for a microprocessor system includes storing interrupts in a pending interrupts register, and storing priority values associated with the stored interrupts in a plurality of priority registers coupled to the pending interrupts register. A plurality of counters coupled in cascade to the plurality of priority registers are loaded with the stored priority values. The loaded priority values are incremented at predetermined intervals, and are compared for identifying the interrupt having a highest priority. The method further includes identifying a respective interrupt service routine to be executed based upon the interrupt having the highest priority.

Abstract: A process for self-aligned manufacturing of integrated electronic devices includes: forming, in a semiconductor wafer having a substrate, insulation structures that delimit active areas and project from the substrate; forming a first conductive layer, which coats the insulation structures and the active areas; and partially removing the first conductive layer. In addition, recesses are formed in the insulation structures before forming said first conductive layer.

Abstract: A decoupling circuit for decoupling conduction lines from each other, the circuit including at least one pass gate element having conduction terminals connected to the conduction lines and having at least one control terminal. The decoupling circuit includes at least one protection circuit inserted between the control terminal and at least one of the conduction lines, and including at least one protection transistor connected to the control terminal and to the at least one conduction line, and configured to take in a disturbing signal passing through the pass gate element (N1) to properly decouple the conduction lines from each other on the occurrence of a disturbing condition.

Abstract: Described herein is an output buffer including an output stage formed by a pull-up transistor and a pull-down transistor, which are connected in series between a supply line set at a supply potential and a ground line set at a ground potential, with an intermediate node connected to the output of the output buffer. The output buffer further includes a unidirectional decoupling stage arranged between the output of the output buffer and the pull-up transistor for decoupling the output from the supply line during the switching transients of the output buffer in such a way as to prevent the switching noise present on the latter from being transferred onto the output of the output buffer.

Abstract: A method for programming a nonvolatile memory cell envisages applying in succession, to the gate terminal of the memory cell, a first and a second programming pulse trains with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next in the first programming pulse train is greater than the amplitude increment between one pulse and the next in the second programming pulse train. The programming method envisages applying, to the gate terminal of the memory cell and before the first programming pulse train, a third programming pulse train with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next may be less than the amplitude increment in the first programming pulse train and substantially equal to the amplitude increment in the second programming pulse train, or else may be greater than the amplitude increment in the first programming pulse train.

Abstract: An integrated power device having a power transistor made up of a first diode and a second diode that are connected together in series between a collector region and emitter-contact region of the power transistor to define a common intermediate node, a control circuit including a high-voltage region bonded on the emitter-contact region (14) by means of an adhesive layer, and biasing circuit connected between the common intermediate node and the high-voltage region. The biasing circuit including a contact pad electrically connected to the common intermediate node, an electrical connection region that is in electrical contact with the high-voltage region (30), and a wire having a first end soldered on the contact pad and a second end soldered on said electrical connection region.

Abstract: A circuit estimates speed of an electromagnetic actuator associated with a reading head of a disk storage unit and a digital controller. The circuit includes first and second supply terminals and an output terminal, with the first supply terminal being connected to the electromagnetic actuator. A measuring resistor is connected to the second supply terminal, and is connected in series with the electromagnetic actuator for measuring a current which passes therethrough when a supply voltage is applied between the first and second supply terminals. An adder has an output connected to the output terminal for providing an output voltage, a first input is connected to the first supply terminal, and a second input is connected to the second supply terminal. An adjustable-gain amplifier is connected between the measuring resistor and the second input of the adder for transferring the supply voltage and a voltage across the measuring resistor to the adder.

Abstract: A device for automatic detection of states of motion and rest includes at least one inertial sensor, having at least one preferential detection axis, and a converter, which is coupled to the inertial sensor and supplies a first signal correlated to forces acting on the first inertial sensor according to the preferential detection axis; the device further includes at least one processing stage for processing the first signal, which supplies a second signal correlated to a dynamic component of the first signal, and at least one threshold comparator, which supplies a pulse when the second signal exceeds a pre-determined threshold.

Abstract: The device includes a circuit for sector remapping having a CAM (Content Addressable Memory) unit, associated to and in data communication with a multiplexer unit. The CAM unit detects that a sector is defective, it provides the pre-programmed address of a replacing sector and it activates the multiplexer which performs the replacement. The defective sectors and the corresponding locations of the address map are therefore advantageously positioned to the rear to the addressing area. The addressing area is consequently continuous, thus allowing the information to be easily stored and retrieved.

Abstract: A multidirectional inertial device having a plurality of preferential detection axes includes: inertial sensors, sensitive to accelerations in a direction parallel to the preferential detection axes; transduction stages, which are coupled to the inertial sensors and supply a plurality of acceleration signals, each of which is correlated to an acceleration parallel to a respective preferential detection axis; a first comparison circuit, which is connected to the transduction stages and supplies a pre-set logic value when at least one of the acceleration signals is greater than a respective upper threshold; and a second comparison circuit, connected to the transduction stages and to the first comparison circuit for supplying the pre-set logic value when each of the acceleration signals is greater than a respective lower threshold, which is smaller than the respective upper threshold.

Abstract: An input digital signal is encoded by subjecting it to a first convolutional coding step followed by an interleaving step and a second convolutional coding step. The serial concatenated convolutional coded signal thus obtained is then subjected to modulation by means of a two-dimensional modulation scheme such as M-PSK or M-QAM. The corresponding decoding process involves an iterative decoding algorithm based on cascaded logarithmic soft-input soft-output processing steps.

Abstract: The electronic device is formed in a die including a body of semiconductor material having a first face covered by a covering structure and a second face. An integral thermal spreader of metal is grown galvanically on the second face during the manufacture of a wafer, prior to cutting into dice. The covering structure comprises a passivation region and a protective region of opaque polyimide; the protective region and the passivation region are opened above the contact pads for the passage of leads.

Abstract: An electronic memory device monolithically integrated in semiconductor has a low pin count (LPC) serial interface. The memory device includes a memory cell array and associated row and column decode circuits. The memory device also includes a bank of T-latch registers to be addressed and accessed in a test mode for serially loading specific test data therein. The serially loading includes activating a test mode of operation by an address storage block for generating a corresponding signal, enabling the bank of T-latch registers in the device to serially receive a predetermined data set, and loading test data into the T-latch registers by using a LPC serial communication protocol.

Abstract: An integration process in a SOI substrate of a semiconductor device having at least a dielectrically insulated well, the process including: an oxidizing step directed to form an oxide layer; a depositing step of a nitride layer onto the oxide layer; a masking step, carried out onto the nitride layer using a resist layer and directed to define suitable photolithographic openings for forming at least one dielectric trench effective to provide side insulation for the well; an etching step of the nitride layer and oxide layer, as suitably masked by the resist layer, the nitride layer being used as a hardmask; a step of forming the at least one dielectric trench, which step comprises at least one step of etching the substrate, an oxidizing step of at least sidewalls of the at least one dielectric trench, and a step of filling the at least one trench with a filling material; and a step of defining active areas of components to be integrated in the well, being carried out after the step of forming the at least one d

Abstract: A driver circuit drives a power element connected to an inductive load. The driver circuit includes an output terminal, and a first current generator is connected between a voltage reference and the output terminal for providing a first charge current to a control terminal of the power element, which is connected to the output terminal. The driver circuit also includes a second current generator connected in parallel with the first current generator. The second current generator is connected between the voltage reference and the output terminal, and provides the control terminal with a second charge current dependent on a voltage present at the input terminal. The input terminal is connected to a conduction terminal of the power element.

Abstract: A manufacturing process of a stacked semiconductor device is described, comprising the following steps: integrating a plurality of electronic devices in a plurality of active areas realized in a semiconductor wafer (9a); distributing an adhesive layer on active areas, splitting the semiconductor wafer into a plurality of first dies, each one comprising at least one of the active areas; mounting the plurality of first dies, which are already equipped with the adhesive layer, on a support; and mounting a plurality of second dies on the adhesive layer. A stacked semiconductor device is also described, which comprises a first die mounted on a support, an intermediate adhesive layer and a second die mounted on the adhesive layer which is a polymeric layer.

Abstract: A method of producing suspended elements for electrical connection between two portions of a micro-mechanism that can move relative to one another provides for the formation of a layer of sacrificial material, the formation of the electrical connection elements on the layer of sacrificial material, and the selective removal of the layer of sacrificial material beneath the electrical connecting elements, the layer of sacrificial material being a thin film with at least one adhesive side that can be applied dry to the surface of the micro-mechanism.

Abstract: A quantum gate for running a Grover's quantum algorithm using a binary function having a vector basis of n qubits is provided. The quantum gate includes a superposition subsystem, an entanglement subsystem and an interference subsystem. The interference subsystem performs an interference operation on components of entanglement vectors for generating components of output vectors. The interference subsystem performs the interference operation in a very fast manner by using an adder receiving as input signals representing even or odd components of an entanglement vector, and generating a sum signal representing a weighted sum with a scale factor of the even or odd components.

Abstract: A power amplification device includes an input for receiving a signal having a desired frequency band. The signal also has a transfer function associated therewith. The power amplification device further includes power amplification circuitry having an order greater than or equal to one, and signal amplifiers connected between the input and the power amplification circuitry. Each signal amplifier has a predetermined gain so that zeros of the transfer function are outside the desired frequency band.

Abstract: A sensing circuit for a memory cell includes a first bias current generator connected between a first voltage reference and a first inner circuit node, and a second reference current generator connected to the first voltage reference. A comparator having a first input terminal is connected to a comparison circuit node that is connected to the second reference current generator, a second input terminal is connected to a circuit node that is connected to the first inner circuit node, and an output terminal forms an output terminal of the sensing circuit. A cascode-configured bias circuit is connected between the inner circuit node and a matching circuit node. The cascode-configured bias circuit is also connected to a second voltage reference. A current/voltage conversion stage is connected to the matching circuit node, to the comparison circuit node, and to a third voltage reference.