Abstract: An apparatus for verifying the data retention in a non-volatile memory is described which comprises at least one multiplexer and at least one shift register. The multiplexer and the at least one shift register are disposed so that the data of the non-volatile memory are in input to the multiplexer the output of which is in turn in input to the at least one shift register. The apparatus comprises a logical circuitry which by suitable commands controls the data transfer from said multiplexer to said at least one shift register, the data loading and the output data shifting in said at least one shift register.

Abstract: Integrated microreactor, formed in a monolithic body and including a semiconductor material region and an insulating layer; a buried channel extending in the semiconductor material region; a first and a second access trench extending in the semiconductor material region and in the insulating layer, and in communication with the buried channel; a first and a second reservoir formed on top of the insulating layer and in communication with the first and the second access trench; a suspended diaphragm formed by the insulating layer, laterally to the buried channel; and a detection electrode, supported by the suspended diaphragm, above the insulating layer, and inside the second reservoir.

Abstract: The circuit system includes an integrated circuit which is one of a family of equivalent integrated circuits that comprises a first-generation integrated circuit operating at the supply voltage of the circuit system and at least one subsequent-generation integrated circuit having a portion operating at a lower voltage. The first-generation integrated circuit has a direct electrical connection between one of the supply terminals and another terminal. The subsequent-generation integrated circuit has a voltage reducer with regulator the output of which is connected to the other terminal. A filter capacitor is connected between the other terminal and one of the supply terminals.

Abstract: The gyroscope is formed by a driving system including a driving mass having an open concave shape; an accelerometer including a sensing mass and comprising mobile sensing electrodes; a linkage connecting the driving mass to the sensing mass. The sensing mass is surrounded on three sides by the driving mass and has a peripheral portion not facing the sensing mass. The mobile sensing electrodes extend integral with the sensing mass from the peripheral portion not facing the driving mass and are interleaved with fixed sensing electrodes. Thereby, there are no passing electrical connections extending below the sensing mass. Moreover the linkage includes springs placed equidistant from the center of gravity of the accelerometer, and the gyroscope is anchored to the substrate with anchoring springs placed equidistant from the center of gravity of the assembly formed by the driving system and by the accelerometer.

Abstract: A micropump includes a body (10) of semiconductor material, accommodating fluid-tight chambers (32), having an internal preset pressure, lower than atmospheric pressure. The fluid-tight chambers (32), sealed by a diaphragm (35) that can be electrically opened, are selectively openable using a first electrode (37) and second electrodes (38), accommodating between them portions of the diaphragm (35).

Abstract: An auxiliary interrupt control circuit is for use in a computer system including at least one peripheral for generating interrupt requests, an interrupt pending register for storing the interrupt requests, a microprocessor for processing interrupts, and an interrupt control circuit associated with the microprocessor. The auxiliary control circuit may include an auxiliary register coupled to the priority interrupt register for storing a copy of the interrupt requests. It may further include an encoder coupled to the auxiliary register and the microprocessor for generating a bit string identifying an active bit stored in the auxiliary register corresponding to a highest priority interrupt request to be processed, and for providing the bit string to the microprocessor.

Abstract: A circuit for detecting a logic transition is proposed.

Abstract: A neuro-fuzzy integrated architecture which permits on-line self-training includes at least one microcontroller of the fuzzy type dedicated to fuzzy rules computing and integrated monolithically on a semiconductor together with a non-volatile memory. Also included within the same integrated circuit are a microprocessor, a volatile memory unit, and an arbiter block linked to a bus interconnecting the fuzzy microcontroller, the microprocessor, and the volatile memory unit. The arbiter block controls access to the memory unit by the microprocessor or the fuzzy microcontroller. An additional fuzzy co-processor may be connected between the fuzzy microcontroller and the microprocessor for performing the fuzzy logic operations.

Abstract: A process for fabricating high-voltage drain-extension transistors, whereby the transistors are integrated in a semiconductor substrate along with non-volatile memory cells that include floating gate transistors.

Abstract: The memory device includes a plurality of memory chips of a certain capacity assembled in a single package and sharing input/output pins, the memories being selectable and singularly enabled one at the time by appropriate external commands coherently with the currently addressed memory location. The device uses only one external enable/disable logic command applied through a single dedicated pin. Each of the memory chips has a number of additional input/output pads equal to 2*n, where 2n is the number of memory chips contained in the device, and a dedicated circuit that generates an internal enable/disable command, as a function of logic inputs corresponding to the logic states of the additional pads and the external enable/disable command.

Abstract: A step-up converter based on an integrated transformer, comprising a self-resonating oscillator circuit that has inductive elements constituted by primary and secondary windings of at least one first transformer, the self-resonating oscillator circuit being powered by an external supply voltage.

Abstract: In order to speed up the search for a data item in the memory and simplify the circuit structure of the memory, with each row of cells there is associated a ground control line, a ground line and a match control line. Furthermore, with every row of cells there is associated a search activation terminal and a match indication terminal.

Abstract: A hybrid vehicle includes an internal combustion engine, an electrical motor, and a drive wheel associated with the electric motor. The drive wheel has a hub, and an axle extending into the hub. The hybrid vehicle also includes a rechargeable battery, and a power circuit for driving the electric motor by drawing power from the rechargeable battery. An electronic torque management unit controls the internal combustion engine and the electric motor. The electric motor is reversible and includes a ferromagnetic pack mounted on the axle for forming a stator within the hub of the drive wheel, and a rotor is mounted adjacent the stator within the hub of the drive wheel.

Abstract: A method of producing a protective inhibitor layer of moisture-generated corrosion for aluminum (Al) alloy metallization layers, particularly in semiconductor electronic devices, includes chemically treating the metallization layer in at least two steps using a mixture of concentrated nitric acid and trace phosphoric acid to produce a thin protective phosphate layer. Alternatively, the method may include dipping the electronic device at least once in a mixture of a polar organic solvent and phosphoric acid (H3PO4) or phosphate derivatives thereof in a low percentage amount (e.g., with a phosphate reactant such as orthophosphoric acid or even R—HxPOy, where R is an alkaline type of ion group or an alkyl radical). The thin film may be formed on top of a thin layer of native aluminum oxide hydrate Al2O3.xH2O.

Abstract: In order to enable interfacing of a microprocessor (1) with a peripheral (3) consisting of a device operating according to high-speed communication specifications (for example, IEEE 1394), it is envisaged that the interface (4) should contain a dedicated memory (40) designed to smooth the delays in communication between the main memory (2) and the peripheral (3). The memory (40) has a trigger (10) that is programmable via software to start a communication when a fraction of the memory (40) or the entire memory (40) is full. When a multiple packet starts to be transferred, a signal is generated to alert the microprocessor (1) of the fact that a transfer is almost completed.

Abstract: A method for forming isolating structures in a silicon carbide layer includes depositing a masking layer on first and second portions of the silicon carbide layer, and forming openings through the masking layer to expose the first portions of the silicon carbide layer. Ions are implanted into the first portions of the silicon carbide layer. The silicon carbide layer is heated to form an oxide layer thereon having first portions on the first portions of the silicon carbide layer, and having second portions on the second portions of the silicon carbide layer. The first portions of the oxide layer are etched to form isolating regions in the silicon carbide layer.

Abstract: A memory device may include a semiconductor substrate, an oxide layer defining spaced apart active areas in the semiconductor substrate, and a floating gate region on each respective active area. The floating gate region may have sidewalls that are slanted with respect to a surface of the semiconductor substrate. Moreover, the memory device may also include a plug in the oxide layer.

Abstract: A nonvolatile memory with a memory array arranged in rows and columns of memory cells in NOR configuration, the memory cells arranged on a same column being connected to one of a plurality of bit lines and a column decoder. The column decoder comprises a plurality of selection stages, each of which is connected to respective bit lines and receives first bit line addressing signals. The selection stages comprise word programming selectors controlled by the first bit line addressing signals and supplying a programming voltage to only one of the bit lines of each selection stage. Each selection stage moreover comprises a string programming selection circuit controlled by second bit line addressing signals thereby simultaneously supplying the programming voltage to a plurality of the bit lines of each selection stage.

Abstract: To obtain frame synchronization and identify the cell codegroup in a cellular communication system (such as a system based upon the standard 3GPP FDD), there are available the synchronization codes organized in chips or letters transmitted at the beginning of respective slots. Slot synchronization is obtained previously in a first step of the operation of cell search. During a second step, there are acquired, by means of correlation or fast Hadamard transform, the energy values corresponding to the respective individual letters with reference to the possible starting positions of the corresponding frame within the respective slot. Operating in a serial way at the end of acquisition of the aforesaid energy values of the individual letters, or else operating in parallel, the energies of the corresponding words are determined. Of these energies only the maximum word-energy value and the information for the corresponding starting position are stored in a memory structure.

Abstract: A hardware quantum gate for running quantum algorithms in a very fast manner exploits the fact that a large number of multiplications required by an entanglement operation of the quantum algorithm provides a null result since only one component per row of the entanglement matrix UF is not a null. The entanglement operation generates an entanglement vector by permuting pairs of opposite components of a linear superposition vector, depending on the value assumed by the function f. More specifically, if function f is null in correspondence to the vector identified by the first (leftmost) n qubits in common with the two n+1 qubit vectors, in which a pair of opposite components of the superposition vector is referred to, then the corresponding pair of components of the entanglement vector is equal to that of the superposition vector, otherwise it is the opposite.