Abstract: A MOS semiconductor device formed on a substrate of a first conductivity type is provided. The device includes active zones for elementary active elements, and at least one inactive zone suitable for electric signal input or output. The substrate is connected with the drain terminal of the device, and at least one of the elementary active elements includes a body region of a second conductivity type that is connected with the source terminal of the device. The at least one inactive zone includes a semiconductor region of the second conductivity type formed in the substrate and adjacent a surface of the substrate, a conductive layer located over the semiconductor region, and a silicon oxide layer located between the semiconductor region and the conductive layer. The silicon oxide layer has alternating first zones and second zones that are contiguous to each other, with the first zones having a greater thickness than the second zones.

Abstract: A method and an electronic device for stabilizing the voltage on the drain terminals of multi-level non-volatile memory cells during programming thereof. The voltage is provided by a drain voltage regulator having an output connected to the drain terminals at a common circuit node by a metal line conduction path having a parasitic intrinsic resistance. A feedback path is advantageously provided between the common circuit node and an input of the regulator.

Abstract: A contact structure for a PCM device is formed by an elongated formation having a longitudinal extension parallel to the upper surface of the body and an end face extending in a vertical plane. The end face is in contact with a bottom portion of an active region of chalcogenic material so that the dimensions of the contact area defined by the end face are determined by the thickness of the elongated formation and by the width thereof.

Abstract: A method and program-load circuit is for regulating the voltages at the drain and body terminals of a non-volatile memory cell being programmed. These voltages are applied from a program-load circuit connected in a conduction pattern to transfer a predetermined voltage value to at least one terminal of the memory cell. The method includes a step of regulating the voltage value locally, within the program-load circuit, to overcome the effect of a parasitic resistor present in the conduction pattern.

Abstract: A microactuator comprises a motor element including a stator and a rotor capacitively coupled to the stator; an actuator element having a circular structure; and a transmission structure interposed between the motor element and the actuator element to transmit a rotary movement of the motor element into a corresponding rotary movement of the actuator element. In particular, the transmission structure comprises a pair of transmission arms identical to each other, arranged symmetrically with respect to a symmetry axis of the microactuator. The transmission arms extend between two approximately diametrically opposed regions of the rotor to diametrically opposed regions of the actuator element.

Abstract: Method of manufacturing an edge structure for a high voltage semiconductor device, including a first step of forming a first semiconductor layer of a first conductivity type, a second step of forming a first mask over the top surface of the first semiconductor layer, a third step of removing portions of the first mask in order to form at least one opening in it, a fourth step of introducing dopant of a second conductivity type in the first semiconductor layer through the at least one opening, a fifth step of completely removing the first mask and of forming a second semiconductor layer of the first conductivity type over the first semiconductor layer, a sixth step of diffusing the dopant implanted in the first semiconductor layer in order to form a doped region of the second conductivity type in the first and second semiconductor layers.

Abstract: A method is described for manufacturing non-volatile memory cells on a semiconductive substrate having active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed and a first layer of conductive material is then deposited. A plurality of floating gate regions are defined by forming stripes of shielding material only above pairs of alternated active areas. Spacers of a selective material are defined with respect to the shielding material and of small width at will in the shelter of the side walls of the stripes thus defined. A shielding material is also deposited on the active areas which lacked it. The formation of the floating gate is completed by leaving the definition of the distance between the floating gate regions to the spacers.

Abstract: A phase-locked loop circuit is proposed for providing an output signal having a frequency depending on the frequency of a reference signal, the circuit including means for deriving a feedback signal from the output signal, means for providing a control signal indicative of a phase difference between the reference signal and the feedback signal, means for controlling the frequency of the output signal according to the control signal, and means for causing the circuit to enter a lock condition when the reference signal and the feedback signal have the same frequency and a pre-defined phase difference. In the circuit of an embodiment of the invention, the means for causing the circuit to enter the lock condition includes means for conditioning the control signal to have an instantaneous value substantially zero in the lock condition by means of a conditioning signal consisting of a series of pulses each one corresponding to the pre-defined phase difference.

Abstract: A method for forming an interface free layer of silicon on a substrate of monocrystalline silicon is provided. According to the method, a substrate of monocrystalline silicon having a surface substantially free of oxide is provided. A silicon layer in-situ doped is deposited on the surface of the substrate in an oxygen-free environment and at a temperature below 700° C. so as to produce a monocrystalline portion of the silicon layer adjacent to the substrate and a polycrystalline portion of the silicon layer spaced apart from the substrate. The silicon layer is heated so as to grow the monocrystalline portion of the silicon layer through a part of the polycrystalline portion of the silicon layer. Also provided is a method for manufacturing a bipolar transistor.

Abstract: A thermal control circuit for an integrated power transistor includes a current generator controlled by a turn on signal, a sensing resistance in series with the power transistor, and a current limiter acting when the voltage drop on the sensing resistance overcomes a certain value. The circuit also includes a current amplifier coupled to the output node of the controlled current generator for outputting a drive current that is injected onto a control node of the power transistor. A soft thermal shut down circuit is provided having a conduction state which is enhanced as the temperature increases for reducing the drive current. The circuit controls the voltage on the power transistor in a more effective manner because the current amplifier has a variable gain controlled by the state of conduction of the soft thermal shut down circuit.

Abstract: A process for transmitting data on a bus, minimizing the switching activity, involves converting the data between a first format and a second format used for transmission of the data. The conversion between said first format and said second format entails the swapping of position of respective bits within a cluster comprising a given number of bits, the swap operation being implementable according to different variants, the maximum number of said variants being equal to the factorial of the aforesaid given number. Each of said variants is identified by a respective pattern. Among the aforesaid patterns, an optimal pattern is selected which minimizes the switching activity at the moment of transmission of data on the bus. The data are then transmitted on the bus using the second format generated using said optimal pattern.

Abstract: A semiconductor substrate has active areas bounded by portions of an insulating layer. A thin layer of tunnel oxide is formed on the substrate and a first layer of conductive material is then deposited. Non-volatile memory cells are manufactured thereon by defining floating gate regions. The definition of these floating gate regions involves defining the first layer of conductive material in order to form a plurality of alternated stripes above pairs of active areas alternated by active areas lacking stripes. Spacers are then formed in the shelter of the side walls of the alternated stripes. A second layer of conductive material is then deposited together with the first layer of conductive material. The spacers are then selectively removed.

Abstract: A memory, particularly but not limitatively a flash memory, comprises at least one data storage area comprising a plurality of data storage locations, and an access circuitry for accessing the data storage locations for either retrieving or altering a data content thereof, depending for example on a memory user request. The memory includes at least one first user-configurable flag element and a second user-configurable flag element. Both the at least one first and the second flag elements are used by a user to set a protected state of the respective data storage area against alteration of the content of the data storage locations thereof. The protected state defined by setting the first flag element is user-removable, i.e., it can be removed by request from the user, so as to enable again the alteration of the content of the data storage area.

Abstract: An architecture for distributing supply voltages to a plurality of memory modules supplied through a plurality of charge pump circuits may include a sorting block bi-directionally connected to the plurality of memory modules, from which it may receive a plurality of power requests. The sorting block may provide a sorting signal based upon a priority scale to drive the plurality of charge pump circuits and distribute supply voltages to the plurality of memory modules. The architecture may advantageously be software-configurable.

Abstract: The present invention relates to a synchronization circuit and method for allowing two or more successive read processes of a memory to be activated simultaneously without destroying the paths or the data. Two independent read processes are mutually independent while active, and are synchronized with respect to each other. The connection between a plurality of sense amplifiers and an output buffer is also synchronized by protocol conditions. The synchronization circuit further synchronizes the read streams so that an evaluation step is perfomed exclusively on one of the plurality of banks of memory while having a plurality of simultaneous read streams.

Abstract: A method for generating a fault signal in a system voltage regulator by a phase signal includes detecting the system voltage and phase signal; comparing the system voltage and phase signal with respective fault levels; and generating a fault signal upon either the system voltage or the phase signal falling below the respective fault level of the fault levels. The fault signal generating method also inhibits generating a fault signal using a drive signal of the system voltage regulator. A diagnostic circuit for a system voltage regulator is also disclosed.

Abstract: The invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organized by the byte in rows and columns, each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line through a selection element of the byte switch type, and each cell being connected to a respective control column through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase.

Abstract: An optical device is formed by a first chip and a second chip bonded together. The first chip (4 has an optical layer of glass housing an optical circuit; the second chip has a body of semiconductor material housing integrated electronic components and coated with a bonding layer of glass fixed directly and contiguous to the optical layer of the first chip. The bonding layer delimits cavities facing corresponding cavities in the first chip in positions corresponding to the intersection points of waveguides constituting the optical circuit. The cavities are filled with a liquid having the same refractive index as the waveguides. Underneath each cavity, in the body of semiconductor material there is present a resistor, which, when traversed by current, causes formation of a bubble inside the chamber and deflection of the light beam traversing a waveguide towards a different waveguide.

Abstract: The present invention relates a Pulse Width Modulation (PWM)/linear driver for an electromagnetic load by a bridge circuit of the type having a signal input and a signal output and at least two conduction control inputs for driving a voice coil motor in a linear mode and in a pulse width modulation. The bridge circuit is driven by a PWM converter coupled to one of said two control inputs and by a linear amplifier coupled to the other of said two control inputs.

Abstract: The voice message managing method for a voice data recording/playing/editing electronic device, said electronic device including a memory device having a first memory area and a second memory area, includes the steps of memorizing, in the first memory area, a plurality of voice messages, and of memorizing, in the second memory area, information regarding the plurality of voice messages. The method also includes the steps of organizing the first memory area as a sequence of blocks, and of memorizing in each block a portion of voice message. The method moreover comprises the steps of defining a list (FBL) containing information on the status of the blocks and memorizing the list in a first memory sub-area of the second memory area, and of defining a table containing a plurality of first vectors associated to respective voice messages and memorizing this table in a second memory sub-area of the second memory area.