Abstract: Digital signals are transmitted on a bus at given instants selectively in a non-encoded format and an encoded format so as to minimize the switching activity on the bus. Given the same value of switching activity, the decision whether to transmit the signals in non-encoded format or in encoded format is taken according to the choice of maintaining constant, without transitions, the value of the additional signal, which signals that encoding of the signals transmitted each time has taken place or has been omitted.

Abstract: A hardware quantum gate for running quantum algorithms in a very fast manner exploits the fact that a large number of multiplications required by an entanglement operation of the quantum algorithm provides a null result since only one component per row of the entanglement matrix UF is not a null. The entanglement operation generates an entanglement vector by permuting pairs of opposite components of a linear superposition vector, depending on the value assumed by the function f. More specifically, if function f is null in correspondence to the vector identified by the first (leftmost) n qubits in common with the two n+1 qubit vectors, in which a pair of opposite components of the superposition vector is referred to, then the corresponding pair of components of the entanglement vector is equal to that of the superposition vector, otherwise it is the opposite.

Abstract: A process for manufacturing an array of cells, including: implanting, in a body of semiconductor material of a first conductivity type, a common conduction region of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings; implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thereby forming control contact regions of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components, each storage component havin

Abstract: The nonvolatile storage device is made up of a memory array divided into a plurality of data-storage units and a plurality of redundancy-storage units for replacing respective failed data-storage units. A control unit detects the functionality of the data-storage units and, in case of failure, enables a redundancy-detection unit having a plurality of volatile-memory elements connected through a sequential daisy-chain connection. A nonvolatile memory unit stores, in a nonvolatile way, the redundancy information through a data bus, connected both to the redundancy-detection unit and to the nonvolatile memory unit; in the event of failure, the redundancy-detection unit transfers the addresses of the failed data-storage unit to the nonvolatile memory unit for their nonvolatile storage.

Abstract: An integrated device for nucleic acid analysis having a support (10) and a first tank (8) for introducing a raw biological specimen includes at least one pre-treatment channel (17), a buried amplification chamber (21), and a detection chamber (24) carried by the support (10) and in fluid connection with one another and with the tank (8). The device can be used for all types of biological analyses.

Abstract: A non-volatile CAM-type memory having a multiplicity of memory cells ordered into a matrix of rows and columns, a word line and a match line associated with every row of cells and a first and a second bit line associated with every column of cells. In order to speed up the search for a data item in the memory and to simplify the circuit structure of the memory, each row of cells is associated with a ground control line and a ground line and every cell also includes a first controlled electronic switch connected between a ground line and a match line associated with the row containing the cell and having a control terminal connected to a match node of the cell and a second controlled electronic switch connected between the match node of the cell and the ground line associated with the row containing the cell, and further having a control terminal connected to the ground control line associated with the row containing the cell.

Abstract: A reconfigurable control structure for CPUs comprises a first control unit with a first basic instruction set associated therewith, and a second control unit, with a second instruction set associated therewith. Associated with the second control unit is at least one programming element for rendering the second instruction set selectively modifiable. Also present is at least one circuit element for supplying instruction codes to be executed to the first control unit and to the second control unit, so that each instruction can be executed under the control of at least one between the first control unit or the second control unit according to whether the instruction is comprised in the first basic instruction set and/or in the second selectively modifiable instruction set.

Abstract: A method for manufacturing circuit structures integrated in a semiconductor substrate that includes regions, in particular isolation regions, includes the steps of:—depositing a conductive layer to be patterned onto the semiconductor substrate;—forming a first mask of a first material on the conductive layer;—forming a second mask made of a second material that is different from the first and provided with first openings of a first size having spacers formed on their sidewalls to uncover portions of the first mask having a second width which is smaller than the first;—partly etching away the conductive layer through the first and second masks such to leave grooves of the second width;—removing the second mask and the spacers; and—etching the grooves through the first mask to uncover the regions provided in the substrate and form conductive lines.

Abstract: An analog input circuit may include a pair of differential transconductance input stages having input nodes connected in parallel and which are fed the analog input signal. One of the differential transconductance stages may have common mode compatibility toward the supply node at the highest potential, and the other stage may have common mode compatibility toward the supply node at the lowest potential. Furthermore, differential output currents of the transconductance input stages may be summed differentially on first and second input nodes of a differential converter stage, which converts the differential current signals to an amplified differential voltage output signal.

Abstract: Method for manufacturing electromagnetic radiation reflecting devices, said method comprising the steps of: a) providing a silicon substrate defined by at least one first free surface, b) forming on said first surface a layer of protective material provided with an opening which exposes a region of the first free surface, and c)etching the region of the free surface by means of an anisotropic agent to remove at least one portion of the substrate and define a second free surface of the substrate inclined in relation to said first surface. Furthermore, said first free surface is parallel to the crystalline planes {110} of silicon substrate and said step (c) comprises a progressing step of the anisotropic agent such that the second free surface resulting from the etching step is parallel to the planes {100} of said substrate.

Abstract: A circuit for biasing an input node of a sense amplifier is proposed. The circuit includes a voltage regulator for keeping the input node at a pre-set operative voltage during a sensing operation. The circuit further includes a pulling device for pulling the input node from a starting voltage towards a power supply voltage, the operative voltage being comprised between the starting voltage and the power supply voltage. The circuit also includes a control device for disabling the pulling device before the input node reaches the operative voltage.

Abstract: A method for amplifying a digital signal representative of data to be transmitted by a line driver with pre-emphasis over an output line is provided. The gain of the line driver is varied between an upper value to coincide with switching of the digital signal and a lower value in absence of the digital signal switching. In particular, the varying includes amplifying the digital signal with a first gain for generating an amplified digital signal, delaying the digital signal with a predetermined delay for generating a delayed digital signal, and amplifying the delayed digital signal with a second gain for generating a delayed and amplified digital signal. An ouput signal corresponding to a difference between the amplified digital signal and the delayed and amplified digital signal is output over the output line.

Abstract: Described is a Design Failure Mode Effect Analysis (DFMEA) Method for analyzing faults and failures in the design phase of electronic apparatus and devices. A data-entry mask is used for recording some information concerning the performed analysis and a portion of the recording form is displayed to a user in an electronic display format.

Abstract: A method is provided for testing an integrated circuit in an automatic test environment. According to the method, the automatic test environment is set up, and there is performed a repetitive measurement of at least one electrical quantity representative of an integrated circuit response to a set of prescribed integrated circuit test conditions. The automatic test environment is reset, and the integrated circuit test conditions are changed in synchrony with a synchronization signal having a prescribed periodicity, so that all of the measurements are allotted a time slot of the same length. Also provided is an automatic test equipment apparatus that includes a synchronization generator for supplying a synchronization signal having a prescribed periodicity to means for putting the integrated circuit in a set test condition. The means changes the set test condition in synchrony with the synchronization signal, so that all of the measurements are allotted a time slot of the same length.

Abstract: Semiconductor power device including a semiconductor layer of a first type of conductivity, wherein a body region of a second type of conductivity including source regions of the first type of conductivity is formed, a gate oxide layer superimposed to the semiconductor layer with an opening over the body region, polysilicon regions superimposed to the gate oxide layer, and regions of a first insulating material superimposed to the polysilicon regions. The device includes regions of a second insulating material situated on a side of both the polysilicon regions and the regions of a first insulating material and over zones of the gate oxide layer situated near the opening on the body region, oxide regions interposed between the polysilicon regions and the regions of a second insulating material, oxide spacers superimposed to the regions of a second insulating material.

Abstract: A semiconductor integrated circuit for processing a plurality of received broadcast signals, such as GPS signals, is operable in two modes: acquisition and tracking. In an acquisition mode, a memory arrangement comprising two circulating shift registers circulates samples of a received signal for correlation with a locally generated version of a GPS code. In a tracking mode, the sampled signal is provided direct to the correlators. The same correlators are thereby used to increase acquisition speed.

Abstract: A resistive structure integrated in a semiconductor substrate and having a suitably doped polysilicon region that is completely surrounded by a dielectric region so that the resistive structure is isolated electrically from other components jointly integrated in the semiconductor substrate.

Abstract: A process for the fabrication of an inertial sensor with failure threshold includes the step of forming, on top of a substrate of a semiconductor wafer, a sample element embedded in a sacrificial region, the sample element configured to break under a preselected strain. The process further includes forming, on top of the sacrificial region, a body connected to the sample element and etching the sacrificial region so as to free the body and the sample element. The process may also include forming, on the substrate, additional sample elements connected to the body.

Abstract: The system carries out conversion of digital video signals organized in blocks of pixels from a first format to a second format. The second format is a format compressed via vector quantization. The vector quantization is performed by means of repeated application of a scalar quantizer to the pixels of said blocks with a quantization step (Q) determined in an adaptive way according to the characteristics of sharpness and/or brightness of the pixels.

Abstract: A method for filtering the noise of a sequence of digital images in CFA format comprising the following phases: