Abstract: A hybrid inductive-capacitive charge pump provided with a driving stage that comprises a step-up converter and a buffer capacitor, and a cascade of charge pump stages; the first stage of the stage cascade is connected to a power supply and the last stage of the stage cascade is connected to an output of the charge pump circuit; the charge pump circuit comprises elements for activating alternately the charge pump stages, transferring charge from one stage of the cascade to the next stage of the cascade, each stage of the cascade of charge pumping stages comprising a pass transistor and a capacitor.

Abstract: A method for the determination of a bias current of a quartz oscillator that includes the phases of: defining a series of bias currents of prefixed values; supplying to said quartz oscillator a bias current value not yet used; verifying the presence of an oscillation signal at the output of said quartz oscillator; supplying in the negative case to said quartz oscillator a bias current value not yet used and repeating the preceding phase; verifying the presence of the correct oscillation frequency; supplying in the negative case a bias current not yet used to said quartz oscillator and repeating the phase of verifying the presence of an oscillation signal at the output of said quartz oscillator; storing, in the positive case, that the supplied current is valid; repeating the preceding phases up to the exhaustion of said series of values of bias currents; fixing as a bias current of said quartz oscillator the algebraic average of the currents regarded as valid.

Abstract: Process for forming salicide on active areas of MOS transistors, each MOS transistor comprising a gate and respective source and drain regions, the source and drain regions each comprising a first lightly doped sub-region adjacent the gate and a second highly doped sub-region spaced apart from the gate. The salicide is formed selectively at least over the second highly doped sub-regions of the source and drain regions of the MOS transistors, and not over the first lightly doped sub-region.

Abstract: A circuit for controlling a reference node in a sense amplifier switchable between an operating mode and a stand-by mode is provided. The reference node provides a reference voltage in the operating mode. The circuit may include circuitry for bringing the reference node to a starting voltage upon entry into the stand-by mode, circuitry for keeping the reference node at a pre-charging voltage in the stand-by mode, and circuitry for providing a comparison voltage closer to the pre-charging voltage than the starting voltage. Pulling circuitry may also be included for pulling the reference node toward a power supply voltage. Further, a controller may activate the pulling circuitry upon entering the stand-by mode, and disable the pulling circuitry when the voltage at the reference node reaches the comparison voltage.

Abstract: The present invention relates a circuit for generating a digital output signal (56) locked to a phase of an input signal (24), comprising a plurality of delay cells (42), a first register (31) containing a first value, a phase detector (26) and a control logic (25), which is characterized by comprising a plurality of flip-flop devices (37, . . . , 38), wherein storing said first value, a second register (30) containing a second value, a plurality of adder nodes (33) adapted to sum in each of said delay cells (42) said second value with the content of said selected flip-flop device (37, . . . , 38), being said delay cells (42) adapted to provide said digital output signal (56), said phase detector (26), receiving said input signal (24) and said digital output signal (56), adapted to detect the phase difference (27) between said input signal and said digital output signal (56), said control logic (25) adapted to control said first and second value in function of said phase difference (27). (FIG.

Abstract: A semiconductor memory system comprising a memory matrix including a plurality of memory cells arranged in rows and columns and connected to a plurality of column lines, each memory cell of the same column having a first and a second terminal connected to a first and a second column line respectively.

Abstract: An MOS device has a stack and a passivation layer covering the stack. The stack is formed by a first polysilicon region and by a second polysilicon region arranged on top of one another and separated by an intermediate dielectric region. An electrical connection region, formed by a column structure substantially free of steps, extends through the passivation layer, the second polysilicon region and the intermediate dielectric region, and terminates in contact with the first polysilicon region so as to electrically contacting the first polysilicon region and the second polysilicon region. Fabrication of the electrical connection region requires just one mask.

Abstract: A system for generating motion vectors in a motion estimator is configured for co-operating with an engine for calculating estimation error for generating motion vectors, according to estimation errors and/or motion vectors previously generated. The system comprises a program memory that contains program data for a motion-estimation algorithm, and a motion-vector memory that contains data identifying said motion vectors previously calculated.

Abstract: The present invention relates to a method and a circuit using the method thereof for minimising the phase errors during the driving of an electric motor, and a circuit using the method thereof, having a stator winding, a permanent magnet rotor assembly, and devices able to sense a rotor position, which comprises the following steps: a) generating of a rotor position signal (10, 14, 39), by means of said devices able to sense said rotor position; b) detecting at least two information from at least two edges (11, 12; 15, 16) of said rotor position signal (10, 14, 39) inside a measure period; c) generating a driving signal (9, 13, 38), in function of said at least two information (11, 12; 15, 16) inside the measure period, so as to follow the rotor velocity.

Abstract: An integrated device having a substrate wherein a buried layer and an epitaxial region have been formed, and an isolation structure adapted to define a plurality of isolation wells for integrating the components of the integrated device therein, the isolation structure including plural dielectrically insulated regions or dielectric trenches being filled with a conductive material to form a plurality of contact regions to buried regions of the device, the buried regions including, in particular, the substrate and buried layer.

Abstract: A bootstrap circuit in DC/DC static converters is provided that includes a power transistor having a first non drivable terminal coupled with a first input voltage and driving means connected with a drivable terminal of the power transistor and adapted for determining the on time and the off time of the power transistor for each prefixed switching time period. The bootstrap circuit includes a capacitor coupled respectively with the second non drivable terminal of the power transistor and with a second input voltage and an input of the driving means so that the voltage between its terminals is substantially equal to the voltage between the second non drivable terminal and the drivable terminal during the off time of the power transistor. The bootstrap circuit includes an overcharge circuit arranged between the second non drivable terminal and ground; the overcharge circuit is able to allow overcharging the capacitor during the off time of the power transistor and for a time period lower than the off time.

Abstract: The manufacturing process comprises the steps of growing epitaxially a first layer from a semiconductor material substrate, forming in the first layer a first and a second buried region spaced from one another and having conductivity of the type opposite that of the first layer; growing epitaxially on the first layer a second layer of semiconductor material having the same type of conductivity as the first layer; forming in the second layer a trench extending in depth beyond the buried regions, arranged between the buried regions, and having, in plan view, a frame shape; forming an oxide layer covering the lateral walls and the base wall of the trench; and filling the remaining part of the trench with an isolating material.

Abstract: An input stage includes switched capacitors for analog-digital converters. The stage comprises a first switched capacitor circuit structure suitable for sampling an analog signal in input to the converter with a preset sampling period, a buffer having in input the analog signal and that can be connected to the first circuit structure by means of a first and a second sampling switch of the first circuit structure coupled respectively with the output terminal and the input terminal of the buffer. The first and the second switch are controlled respectively by a first and a second signal to close respectively for a first interval of time and for a successive second interval of time of a first semi-sampling period of the analog signal.

Abstract: A method of reading and restoring data stored in a ferroelectric memory cell is disclosed. The cell includes a first transistor and first ferroelectric capacitor connected, in series with each other, between a first bitline and an auxiliary line, a second transistor and second ferroelectric capacitor connected, in series with each other, between a second bitline and the auxiliary line, the first and second transistors having respective control terminals connected to a common wordline. The reading method includes precharging the first and second capacitors, applying a read pulse to the cell such that the state of the first capacitor is changed, reading the cell by a sensing means, and restoring the first capacitor to an initial state.

Abstract: In a method for multiplication of floating-point real numbers, encoded in a binary way in sign, exponent and mantissa, the multiplication of the mantissa envisages a step of calculation of partial products, which are constituted by a set of addenda corresponding to the mantissa. In order to reduce the size and power consumption of the circuits designed for calculation, there is adopted a method of binary encoding which envisages setting the first bit of the mantissa to a value 1, in order to obtain a mantissa having a value comprised between 0.5 and 1. Also proposed are methods for rounding of the product and circuits for the implementation of the multiplication method. Also illustrated are circuits for conversion from and to encoding of floating-point real numbers according to the IEEE754 standard. Preferential application is in portable and/or wireless electronic devices, such as mobile telephones and PDAs, with low power-consumption requirements.

Abstract: A memory system comprising a semiconductor memory for storing digital data, said memory being connectable to a control device in order to receive an address signal and to make data selected through the output-available address signal. The system is characterised in that it comprises a generating circuit for activating a wait signal to be forwarded to the control device during reading operations in such a way as to indicate the non-availability of the data to be read. The generating circuit is such to deactivate the wait signal, in such a way as to indicate the availability of the data to be read, following a waiting time interval correlated with an effective access time for said memory.

Abstract: A lateral-current-flow integrated transistor, formed in an epitaxial layer defining a base well with a first conductivity type, which accommodates emitter and collector regions of a second conductivity type. The collector region is formed by an internal conductive region and by an external conductive region, and the emitter region is formed by an intermediate conductive region. The external conductive region has an annular shape and surrounds the intermediate conductive region, which also has an annular shape and surrounds the internal conductive region.

Abstract: A regulated voltage-boosting device provides a charge-pump circuit, which has an input terminal receiving a first voltage and an output terminal supplying a second voltage higher than the first voltage. The regulated voltage-boosting device provides a plurality of voltage-boosting stages that can be selectively activated and deactivated. The regulated voltage-boosting device provides an automatic-selection circuit for activating a number of voltage-boosting stages which is correlated to the first voltage and to the second voltage.

Abstract: A cryptation system for information transmitted through packet switching networks masks the digital information data by combining it at the transmitting station with digital data of a certain cryptation code before transmitting the so-encrypted data through the network. The system also performs an inverse decrypting processing at the receiving station using the same code. The system generates at a transmitting station and at a receiving station, starting from a given pair of password codes or user key, a certain discrete chaotic model or map of the pair of codes or key, producing dynamically updated pairs of values of codes or keys every certain number of processing steps of the chaotic map. The data to be transmitted is masked by way of a logic combination with the current dynamically updated keys at the transmitting station.

Abstract: Described herein is a method for compressing a sequence of repetitive data, which uses in combination one or more words with a format for non-compressible data and one or more words with a format for compressible data, in which a word with a format for non-compressible data is made up of a set of bits, in which the most significant bit is set at the logic value “1” and the remaining bits are the bits of a non-compressible datum to be encoded, whilst a word with a format for compressible data is made up of a set of bits, in which the most significant bit is set at a the logic value “0”, the next five most significant bits indicate the total number of subsequent words which encode the sequence of repetitive data, and the remaining eleven bits indicate the number of times that the words indicated by the preceding five most significant bits are repeated.