Abstract: A circuit for detecting signals present on a bifilar voltage-supply and signal-transmission line, in which the signals are constituted by positive and negative variations of the supply potential of at least one of the wires of the line, the circuit including a low-pass filter connected to the two wires of the line in order to supply, at an output terminal of the filter, a constant reference potential substantially equal to the supply potential of a preselected one of the two wires, a first threshold comparator having a reference input terminal and a threshold input terminal connected, respectively, to the output terminal of the filter and to the preselected wire of the two wires, and a second threshold comparator having a reference input terminal and a threshold input terminal connected, respectively, to the preselected wire of the two wires and to the output terminal of the filter.

Abstract: A telephone receiving section having a final stage, an electroacoustic transducer having a first terminal connected to the ground of the circuit, a unit for controlling switching on/off, a source of a reference voltage, a switch that can adopt a first position or a second position in order to connect the second terminal of the transducer selectively, via a capacitor, to a reference-voltage terminal of the reference voltage source or to an output terminal of the final stage, respectively, and control means that respond to signals of the unit for controlling switching on/off in order to activate or to deactivate the final stage and the reference-voltage source and to operate the switch in accordance with a predetermined time program. The receiving section operates with the same immunity to disturbances as a fully balanced structure, even though the transducer is not connected between two balanced outputs.

Abstract: The integrated structure and process is effective to form, in a dielectrically insulated well, a MOS component including respective drain and source regions of a first conductivity type as well as a gate region. The integrated structure includes a cut-off layer of the second conductivity type effective to surround only the source region. The cut-off layer is self-aligned by the gate region.

Abstract: The method applies to non-volatile semiconductor memories with cells arranged in rows and in columns, in which each cell has a first terminal, a second terminal, and a third terminal connected, respectively, to a row line, to a column line, and to a common node by respective connection strips. In order to form connections with low resistivity and consequently to save semiconductor area, the method provides for the formation of an oxide layer which covers the connection strips of the first terminals and of the third terminals, the formation of channels along the connection strips until the surfaces thereof are exposed, and the filling of the channels with a material having a resistivity lower than that of the connection strips.

Abstract: A method of programming a plurality of memory cells are connected in parallel between first and second supply references and having their gate terminals connected together and, through row decoding means, also connected to an output terminal of an operational amplifier that is adapted to generate a word voltage signal, the first voltage reference being provided by a charge pump circuit. The programming method uses a program loop that includes the cells to be programmed and the operational amplifier, the charge pump circuit thus outputting a voltage ramp whose slope is a function of the cell demand. A programming circuit adapted to implement the method is also provided.

Abstract: A non-volatile semiconductor memory device including an output connected to a row line and two supply terminals. Each elementary stage has an upper branch with a p-channel MOS transistor and a lower branch with an n-channel MOS transistor. In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor in the upper branch and a p-channel transistor in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.

Abstract: A capacitor for sensing a substrate voltage in an integrated circuit power device may be implemented by isolating a portion or segment of the metal layer that normally covers the heavily doped perimeter region typically used for electric field equalization. In conjunction, one or more portions of an isolation dielectric layer of silicon oxide are not removed from the surface of the semiconductor substrate, as is commonly done before depositing the metal layer. The portions of isolated silicon oxide which are not removed become the dielectric layer of the capacitor. Moreover, one plate of the capacitor is formed by the heavily doped perimeter region that is electrically connected to the substrate (e.g. a drain or collector region). The other plate is formed by the segment of metal isolated from the remaining metal layer defined directly over the heavily doped perimeter region.

Abstract: A nonvolatile memory having a NOR architecture has a memory array including a plurality of memory cells arranged in rows and columns in NOR configuration, the memory cells arranged on a same column being connected to one of a plurality of bit lines; and a column decoder. The column decoder comprises a plurality of selection stages, each of which is connected to respective bit lines and receives first bit line addressing signals. The selection stages comprise word programming selectors controlled by the first bit line addressing signals and supplying a programming voltage to only one of the bit lines of each selection stage. Each selection stage moreover comprises a string programming selection circuit controlled by second bit line addressing signals thereby simultaneously supplying the programming voltage to a plurality of the bit lines of each selection stage.

Abstract: A method and circuit for accessing a memory location comprising at least one respective ferroelectric storage unit of a matrix of ferroelectric storage units, the memory location is selected by connecting a first terminal of a ferroelectric storage element of the at least one respective storage unit to a respective access line to the memory location; at least another memory location to which is not intended to be accessed is also selected. A second terminal of the ferroelectric storage element is biased to a prescribed access electric potential, and an electric potential on the access line is sensed; the second terminal of the ferroelectric storage elements of the other memory location is also biased to the access potential.

Abstract: An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area. The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

Abstract: Testing a CMOS integrated circuit includes establishing a current threshold value, powering the integrated circuit in static and idle conditions, measuring the current absorbed by the integrated circuit and comparing this with the threshold value and accepting or rejecting the integrated circuit if the comparison shows that the current absorbed measured is respectively lower or higher than the threshold value. To improve discrimination between non-faulty and faulty devices, the threshold value is obtained by forming two measurement transistors in the integrated circuit, one n channel and the other p channel, biasing these in the cut-off zone and measuring their sub-threshold currents.

Abstract: A circuit for the speed recovery of a direct current motor includes an output stage, output stage having a first pair of transistors, a second pair of transistors, and means a first circuit configured to detect a current circulating in the motor. The output stage further includes a second circuit configured to, activate the second pair transistors for a determined first time period so as to short-circuit the motor, and, at the end of the first time period, unbalance the output stage so as to force a maximum current to circulate for a determined second time period as a function of a value detected by the first circuit during the first time period, so as to stop the motor.

Abstract: Bandgap type reference voltage source using an operational transimpedance amplifier. The bandgap stage is formed by a first and a second bandgap branch parallel-connected; the first bandgap branch comprises a first diode and a transistor, series-connected and forming a first output node; the second bandgap branch comprises a second diode and a second transistor series-connected and forming a second output node. The operational amplifier has inputs connected to the output nodes of the bandgap stage. An amplifier current detecting stage is connected to the outputs of the operational amplifier and supplies a current related to the current drawn by the operational amplifier. A diode current detecting stage is connected to the output of the amplifier current detecting stage and to an output of the operational amplifier and supplies a current related to the current flowing in the first diode. An output stage transforms this current into a stabilized voltage.

Abstract: A start-detection circuit and a stop-detection circuit detect the start condition and the stop condition in a data signal associated with a clock signal according to the IIC protocol. The start-detection circuit comprises: a first detector to produce a first reset signal when a trailing edge of the data signal is detected; a counter to count pulses of a reference signal when the first reset signal is received, and to produce an enabling signal when the number of pulses counted has reached a predefined number; a second detector to store the enabling signal when a trailing edge of the clock signal is detected. The stop-detection circuit comprises a third detector to produce a stop signal when a leading edge of the data signal is detected after the detection of a leading edge of the clock signal.

Abstract: A non-volatile memory device including a plurality of memory cells, each memory cell formed as MOS transistor with a source region, a drain region and a gate having sides formed therewith; and one or more dielectric spacers disposed on the sides of the gate. At least one memory cell is defined in an ON state and at least one memory cell is defined in an OFF state. The memory cells in the ON state comprise drain regions and source regions of the lightly diffused drain (LDD) type, characterized in that the at least one drain region and the at least one source region of the memory cells in the OFF state are formed by one or more high dopant regions. The memory cells in the OFF state consists of layers of silicide on top of one or more active regions defined as the source region, the drain region, and the gate.

Abstract: The invention relates to a monolithically integrated telephone circuit for driving wide-band telephone lines and transmitting digital data at a very high frequency. The telephone circuit is powered from a battery DC supply providing a pair of voltage references. The telephone circuit includes an output circuit portion including a pair of differential output stages, each having a pair of inputs and being connected with its output to a respective lead of a two-wire telephone line. The telephone circuit also includes a device for deriving a reference voltage from the supply voltage, and includes a low-voltage supply network which is input a DC signal and produces a voltage reference to be added to the reference voltage for delivery to one input of each output stage. The other input of each stage receives an AC signal in order to present at the circuit output a suitable AC+DC differential voltage for driving the telephone line.

Abstract: A circuit implementing a non-integer order dynamic system includes a neural network that receives at least one input signal and generates therefrom at least one output signal. The input and output signals are related to each by a non-integer order integro-differential relationship through the coefficients of the neural network. A plurality of such circuits, implementing respective non-integer order controllers can be interconnected in an arrangement wherein any of the integral or differential blocks included in one of these circuits generates a signal which is fed to any of the integral or differential blocks of another circuit in the system.

Abstract: A contact structure for a ferroelectric memory device integrated in a semiconductor substrate and includes an appropriate control circuitry and a matrix array of ferroelectric memory cells, wherein each cell includes a MOS device connected to a ferroelectric capacitor. The MOS device has first and second conduction terminals and is covered with an insulating layer. The ferroelectric capacitor has a lower plate formed on the insulating layer above the first conduction terminals and connected electrically to the first conduction terminals, which lower plate is covered with a layer of a ferroelectric material and coupled capacitively to an upper plate. Advantageously, the contact structure comprises a plurality of plugs filled with a non-conductive material between the first conduction terminals and the ferroelectric capacitor, and comprises a plurality of plugs filled with a conductive material and coupled to the second conduction terminals or the control circuitry.

Abstract: A memory device includes an internal address bus, and first and second internal data busses. A memory receives from the internal address bus an address of memory data to be read, and transfers read memory data in blocks of N bits to the first internal data bus. An address storing circuit is coupled to the internal address bus for storing the address of the memory data to be read. An array of latches is coupled to the first internal data bus for storing the read memory data received therefrom. The array of latches includes two banks of latches. Each bank has N latches and is controlled independently from the other bank by respective commands, and each bank stores bits present on the first internal data bus upon receiving the respective commands. The second internal data bus is also connected to the array of latches.

Abstract: A multiplier circuit which multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are applied to input terminals of logic gating circuits. The logic gating circuits provide partial products of the bits of the two binary numbers, and a combinatorial network provides the final sum of the partial products. The partial products that include at least one of the more significant bits of either of the operands are performed by logic gating circuits which can be enabled to complement the partial product. The multiplier circuit further includes additional logic gating circuits which supply the combinatorial network with additive constants with predetermined logic values.