Abstract: A generator circuit for voltage ramps is provided that includes a differential stage with positive feedback coupled between a first and a second voltage reference and having a first output connected to a control terminal of a first output transistor. The first output transistor is connected at an output terminal of the ramp generator circuit to a capacitive charge to be biased with voltage ramps. The ramp generator circuit also includes a second output transistor parallel connected to the first output transistor and having the control terminal connected to a second output of the differential stage.

Abstract: A sense amplifier for a memory includes a comparator and a bit line polarization circuit. The comparator receives a first signal representative of a current flowing through a memory cell and a second signal representative of a reference current. Additionally, the comparator includes a stage in a common source configuration and an active load for the stage, and the bit line polarization circuit provides a polarization voltage level that is independent of the supply voltage level. In a preferred embodiment, the sense amplifier also includes an output stage that improves switching time at high supply voltages.

Abstract: The converter uses the energy stored in the output filter of a step-down (or buck) converter and in the inductor of a step up/down (or buck-boost) converter to supply a second output of opposite sign. In particular, the converter has a first input receiving an input voltage; a first output supplying a first output voltage of a first sign; a second output supplying a second output voltage of opposite sign; a controlled switch connected between the first input and a first intermediate node; an inductor connected between the first intermediate node and the first output; a diode connected between the first intermediate node and a second intermediate node; and a dual voltage generating circuit connected between the second intermediate node and the second output.

Abstract: The voltage generator comprises a negative feedback loop including a programmable voltage divider having a feedback node. The voltage divider comprises a programmable resistor disposed between the output of the voltage generator and the feedback node and having variable resistance. The programmable resistor includes a fixed resistor and a plurality of additional resistors arranged in series with each other and defining a plurality of intermediate nodes. The additional resistors may be selectively connected by means of switches disposed between the output of the voltage generator and a respective intermediate node so as to define an output voltage V0 programmable on the basis of command signals supplied to the switches.

Abstract: The boost device comprises a charge pump circuit having an input and a main output between which an input stage, an intermediate stage and a main output stage are cascade connected. The charge pump circuit also comprises a stand-by output stage having an input node connected to an output node of said intermediate stage and an output node connected to a stand-by output of the charge pump circuit. The boost device further comprises a phase generator stage having a signal input receiving a suitable clock signal generated by a clock generator stage and output terminals generating phase signals supplied to phase inputs of the charge pump circuit.

Abstract: The method for authentication and electronic signature is of the private-key, challenge and response type between a user requesting an authorization, via, for example, a smart card and a controller—check terminal—supplying the authorization. To increase security of the authorization or authentication operations, the smart card comprises a chaotic generator generating user's acknowledgement code, which is compared with a comparison code generated by the check terminal using a chaotic generator which is the same.

Abstract: A polymeric composition for making semiconductor device packaging includes at least one epoxy resin, at least one curing agent in an amount between 30 and 110 parts by weight per 100 parts by weight of the epoxy resin, at least one silica-based reinforcing filler in an amount between 300 and 2300 parts by weight per 100 parts of the epoxy resin, and at least one control agent for a rheology of the polymeric composition. The at least one control agent may be substantially free from polar groups and present in an amount between 0.1 and 50 parts by weight per 100 parts by weight of the epoxy resin. The invention also relates to a plastic packaging material for microelectronic applications which may be obtained from the above polymeric composition, and to a semiconductor electronic device including such packaging material.

Abstract: The data management method applies to a multilevel nonvolatile memory device having a memory array formed by a plurality of memory cells. Each of the memory cells stores a number of bits that is not an integer power of two, for example three. In this way, one data byte is stored in a non-integer number of memory cells. The managing method includes storing, in a same clock cycle, a data word formed by a plurality of bytes, by programming a preset number of adjacent memory cells. Reading is performed by reading, in a same clock cycle, the stored data word.

Abstract: A resistive structure integrated on a semiconductive substrate is described. The resistive structure has a first type of conductivity formed into a serpentine region of conductivity which is opposite to that of the semiconductive substrate. In at least two parallel portions of the serpentine region, there is at least one trench filled with an insulating material.

Abstract: The method for reading a memory cell is based upon integration in time of the current supplied to the memory cell by a capacitive element. The capacitive element is initially charged and then discharged linearly in a preset time, while the memory cell is biased at a constant voltage. In a first operating mode, initially a first capacitor and a second capacitor are respectively charged to a first charge value and to a second charge value. The second capacitor is discharged through the memory cell at a constant current in a preset time; the first charge is shared between the first capacitor and the second capacitor; and then the shared charge is measured.

Abstract: A method of erasing a flash memory integrated in a chip of semiconductor material and including at least one matrix of cells with a plurality of rows and a plurality of columns made in at least one insulated body, the cells of each row being connected to a corresponding word line; the method includes the step of applying a single erasing pulse relative to a selected single one of the at least one body to a selected subset of the word lines for erasing the cells of each corresponding row made in the selected body with no intermediate check of the completion of the erasure.

Abstract: A circuit structure integrated in a semiconductor substrate comprises at least one pair of transistors each being formed each in a respective active area region and having a source region and a drain region, as well as a channel region intervening between the source and drain regions and being overlaid by a gate region. The gate regions are connected electrically together by an overlying conductive layer and respective contacts. The contacts between the gate regions and the conductive layer are formed above the active areas.

Abstract: A method of controlling the quantity and uniformity of distribution of bonded oxygen atoms at the interface between the polysilicon and the monocrystalline silicon includes carrying out, after having loaded the wafer inside the heated chamber of the reactor and evacuated the chamber of the LPCVD reactor under nitrogen atmosphere, a treatment of the wafer with hydrogen at a temperature generally between 500 and 1200° C. and at a vacuum generally between 0.1 Pa and 60000 Pa. The treatment is performed at a time generally between 0.1 and 120 minutes, to remove any and all the oxygen that may have combined with the silicon on the surface of the monocrystalline silicon during the loading inside the heated chamber of the reactor even if it is done under a nitrogen flux. After such a hydrogen treatment, another treatment is carried out substantially under the same vacuum conditions and at a temperature generally between 700 and 1000° C. with nitrogen protoxide (N2O) for a time generally between 0.

Abstract: Bandgap voltage reference circuit with an output voltage that remains stable in the range of a temperature of utilization. The circuit includes a first circuit block, a second circuit block, and a control circuit connected with said circuit blocks, said first circuit block including a bandgap circuit with a low power consumption, said second circuit block including a bandgap circuit with a short start up time, said control circuit suitable to control said two circuit blocks in a such way that said output voltage of said bandgap voltage reference circuit is supplied by said second circuit block at the starting of said first circuit block for a period of time and said output voltage is supplied by said first circuit block for the period of time subsequent to said period of time and that lasts until the turning off of the circuit, said second circuit block being turned off after said period of time.

Abstract: An SMPS converter with an inductor connected in series to the standard inductor present in the output filter to form an inductive divider supplying an intermediate voltage having an amplitude greater than the output voltage. The intermediate voltage is supplied to a capacitor that stores the voltage during the conduction phase of the integrated circuit that forms the switch of the converter and transfers the voltage during opening of the integrated circuit to a capacitor connected between the output and the supply input of the integrated circuit.

Abstract: A current reference circuit for low supply voltages is provided. The current reference circuit includes a series including a resistor and a diode, a current source having one terminal coupled to a supply voltage and another terminal coupled to the series, an operational amplifier having its negative electrode connected to a band gap reference voltage, and a transistor. The diode has its cathode electrode coupled to ground and its anode electrode coupled to the resistor. The transistor has its gate electrode coupled to the output of the operational amplifier, its source electrode coupled to ground, and its drain electrode coupled to both the positive electrode of the operational amplifier and the current source. Also provided are an integrated circuit that includes at least one current reference circuit for low supply voltages and a signal processing system that includes at least one current reference circuit for low supply voltages.

Abstract: The manufacture process includes: forming a first wafer of semiconductor material housing integrated electronic components forming a microactuator control circuit and a signal preamplification circuit; forming microactuators, each including a rotor and a stator, in a surface portion of a second wafer of semiconductor material; attaching the second wafer to the first wafer, with the surface portion of the second wafer facing the first wafer; thinning the second wafer; attaching the second wafer to a third wafer to obtain a composite wafer; thinning the first wafer; cutting the composite wafer into a plurality of dice connected to a protection chip; removing the protection chip; attaching read/write transducers to the dice; and attaching the dice to supporting blocks for hard-disk drivers.

Abstract: The method for reading a memory cell includes supplying the cell with a first charge quantity through a capacitive integration element and reintegrating the first charge quantity through a plurality of second charge quantities supplied alternately and in succession to the capacitive integration element. In a first embodiment, the second charge quantities are initially stored in a plurality of capacitive charge-regeneration elements connected alternately and in succession to the capacitive integration element; the second charge quantities are then shared between the capacitive integration element and the capacitive charge-regeneration elements.

Abstract: The process for the fabrication of an electronic device has the steps of forming a layer to be etched on top of a substrate in a wafer of semiconductor material; depositing a masking layer; and carrying out a plasma etch to define the geometry of the layer to be etched. The masking layer is made so as to be conductive, at least during one part of the etching step; in this way, the electrons implanted on the top part of the masking layer during plasma etching can recombine with the positive charges which have reached the layer to be etched. The recombination of the charges makes it possible to prevent damage from plasma resulting from the formation of parasitic electric currents which are detrimental to the electronic device itself.

Abstract: A word line selector for selecting word lines of an array of semiconductor memory cells formed in a doped semiconductor region of a semiconductor substrate comprises a plurality of word line drivers responsive to word line selection signals. Each word line driver is associated with a respective word line for driving the word line to prescribed word line electric potentials, depending on an operation to be conducted on the array of memory cells, in accordance with the word line selection signal.