Abstract: A converter circuit for performing transfer of control logic signals between a first device and a second device in connection with an interconnection bus, the first device operating at the frequency of a first clock signal and the second device operating at the frequency of a second clock signal. The clock frequencies may be in a first ratio to one another corresponding to unity, as well as in a second and a third ratio. The converter circuit includes manipulation circuit elements which define respective propagation paths through the converter circuit for control signals. A logic network may assume three states, corresponding, respectively, to the first, second and third ratios between the frequencies of the clock signals, selectively interposing the manipulation elements in the propagation paths.

Abstract: A method of compressing digital images acquired in CFA format that utilizes optimized quantization matrices. The method, basing itself on the statistical characterization of the error introduced during the processing phase that precedes compression, appropriately modifies the coefficients of any initial quantization matrix, even of a standard type, obtaining a greater compression efficiency without introducing further quality losses.

Abstract: A method for reducing the settling time in PLL circuits, particularly for use in an RF transceiver, the PLL circuits including a phase comparator, a filter, a digital-analog converter and an adder that are suitable to produce in output a voltage (VC) for controlling a voltage-controlled oscillator provided by means of a varactor, the method including determining the dependency of the control voltage (VC) of the voltage-controlled oscillator on the frequency of a selected channel of a transmitter; and generating a law describing the variation of the output current (IDAC) of the digital-analog converter such that the voltage (VDAC) obtained from the output current of the digital-analog converter, added to an output voltage (Vf) of said filter keeps the filter voltage (Vf) constant in order to reduce the settling time of the PLL circuit as a selected channel varies.

Abstract: A contact structure for a ferroelectric memory device integrated in a semiconductor substrate and includes an appropriate control circuitry and a matrix array of ferroelectric memory cells, wherein each cell includes a MOS device connected to a ferroelectric capacitor. The MOS device has first and second conduction terminals and is covered with an insulating layer. The ferroelectric capacitor has a lower plate formed on the insulating layer above the first conduction terminals and connected electrically to the first conduction terminals, which lower plate is covered with a layer of a ferroelectric material and coupled capacitively to an upper plate. Advantageously, the contact structure comprises a plurality of plugs filled with a non-conductive material between the first conduction terminals and the ferroelectric capacitor, and comprises a plurality of plugs filled with a conductive material and coupled to the second conduction terminals or the control circuitry.

Abstract: A method of arbitration among a plurality of n units which seek access to a resource is regulated according to grants identified by means of an arbitration method, which compares between one another the priorities, generating, for each pair of the units comprising in general a unit x and a unit y with respective priorities Px and Py, a selection signal at a high level if the result of the operation Px>=Py is true. The method generates, for the pairs of the units, respective cross-request signals and generates the grant for the ith unit as a logical product of all the cross-request signals req_i_z with z ranging from 1 to n, excluding the case of z=i.

Abstract: A process for fabricating a VDMOS power transistor includes forming a gate overlying at least one channel region in a semiconductor substrate, and forming spacers on a first portion of the semiconductor substrate self-aligned with the gate. A first dopant is implanted into the exposed portion of the semiconductor substrate for defining a body region of the transistor. The first dopant is implanted through a first implant window defined by the spacers. The spacers are removed, and a second dopant is implanted into the first portion of the semiconductor substrate for defining a source region of the transistor. The second dopant is implanted through a second implant window defined by an edge of the gate.

Abstract: A processing unit with balanced outputs transfers a received digital signal to an amplification unit with balanced inputs and outputs. A control unit enables or disables the processing and amplification units in response to a power up/power down signal. To prevent disturbances due to power up/power down transients from appearing in a speaker connected between the outputs of the amplification unit, switches are provided between the outputs of the processing unit and the inputs of the amplification unit. A delay circuit generates according to a predetermined timing program enabling/disabling control signals for the processing and amplification units, and generates control signals for the switches.

Abstract: A method of estimating the motion field of a digital picture sequence includes subdividing a current picture to examine in an integer number of macroblocks, for each macroblock of the current picture determining a search window centered on a macroblock of a preceding picture placed in the same position of the considered macroblock of the current picture, carrying out a motion estimation between the considered macroblock of the current picture and the macroblock most similar to it included in the window. At least a dimension of the search window is established as a function of the corresponding dimension of the search window used for the preceding picture, the estimated motion field of the preceding picture and certain threshold values.

Abstract: The present invention relates a monostable circuit adapted to provide a delay having a length inversely proportional to an input signal, characterized by comprising generating means (21, 22) adapted to generate a signal proportionally to an input signal (Vin) and to a corrective factor (35), comparing means (23) adapted to compare the value of said signal with a prefixed value range (Imin, Imax) and correcting means (24) adapted to correct said corrective factor (35) in the case that the value of said signal is out of said prefixed value range (Imin, Imax).

Abstract: A blood pressure Holter system includes a pneumatic constriction sleeve to be worn on an arm of the user and includes a first sensor for acquiring systolic and diastolic values of arterial pressure of the user. A second sensor is carried adjacent a chest of the user for sensing movement of the user's body. The system further includes a detection and classification circuit for detecting and classifying movement of the user's body for producing an index of a state of physical exertion corresponding to systolic and diastolic values of arterial pressure. A fuzzy logic controller processes the systolic and diastolic values of arterial pressure using fuzzy logic.

Abstract: A method of depositing a dielectric ply structure to optimize the planarity of electronic devices that include a plurality of active elements having gate regions laid across the substrate as discrete parallel lines, such as the bit lines of memory cells. In accordance with the principles of the present invention, the plurality of bit lines may be isolated from one another by the dielectric ply structure to provide a planar architecture onto which an optional conductive layer may be deposited. The resulting planarization avoids the typical shortcomings of the prior art, such as the lack of electrical continuity in the word lines or their excessively high electrical resistance from slenderized portions in the conductive sections due to poor planarity of the surfaces upon which the conductive layer is deposited.

Abstract: The phase-change nonvolatile memory array is formed by a plurality of memory cells extending in a first and in a second direction orthogonal to each other. A plurality of column-selection lines extend parallel to the first direction. A plurality of word-selection lines extend parallel to the second direction. Each memory cell includes a PCM storage element and a selection transistor. A first terminal of the selection transistor is connected to a first terminal of the PCM storage element, and the control terminal of the selection transistor is connected to a respective word-selection line. A second terminal of the PCM storage element is connected to a respective column-selection line, and a second terminal of the selection transistor is connected to a reference-potential region while reading and programming the memory cells.

Abstract: On a semiconductor material body housing an electronic device a peripheral region of semiconductor material and at least one pad are initially formed. The peripheral region is connected to a first terminal of the electronic device and extends on at least one peripheral portion of the semiconductor material body. The pad is insulated from the semiconductor material body and is electrically connected to a second terminal of the electronic device. The semiconductor material body is fixed to a support body formed by a blank belonging to a reel. The pad is connected by a wire to an electrode formed by the blank. Next, a connection region is formed on the peripheral region and surrounds, at least partially, the semiconductor material body and the support body. The connection region is advantageously obtained by galvanic growth.

Abstract: A resonant driving system for a fluorescent lamp having one end connected to a primary winding of a transformer. The driving system includes an inductor inserted between an input section of the resonant driving system and an internal circuit node that is connected to another end of the fluorescent lamp a converter inserted between the internal node and a voltage reference and comprising a first transistor and a second transistor of the complementary type, inserted, in series to each other, between the internal node and the voltage reference, and a control circuit connected to a secondary winding of the transformer and to the converter as well as to the control terminals of the first and second transistors of the converter, wherein the control circuit comprises an inductor connected to a resistor that is connected to the control terminals of the first and second transistors through a first and a second capacitor respectively.

Abstract: A voltage/current controller device, particularly for interleaving switching regulators, comprises: a DC/DC converter having a plurality of modules, with each module including a drive transistor pair connected in series between first and second supply voltage references, a current sensor connected to one transistor in the pair, and a current read circuit connected to the sensor. Advantageously, the read circuit comprises a transconductance amplifier connected across the current sensor to sense a voltage signal related to a load current being applied to each module, the transconductance amplifier reading the voltage signal with the transistor in the conducting state.

Abstract: A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the semiconductor substrate, and a plurality of memory cells in a third portion of the semiconductor substrate. A matrix mask used for selectively removing a dielectric layer from the first and third portions of the semiconductor substrate allows dielectric to remain on a floating gate of the plurality of memory cells and on the gate electrodes of the plurality of first transistors. A control gate is then formed on the floating gate, which is separated by the dielectric. Portions of the gate electrodes for the plurality of first transistors are left free so that contact is made with the transistors.

Abstract: Presented is a memory cell integrated in a semiconductor substrate that includes a MOS device connected in series to a capacitive element. The MOS device has first and second conduction terminals, and the capacitive element has a lower electrode covered with a layer of a dielectric material and capacitively coupled to an upper electrode. The MOS device is overlaid by at least one metallization layer that is covered with at least one top insulating layer. The capacitive element is formed on the top insulating layer. The cell is unique in that the metallization layer extends only between the MOS device and the capacitive element.

Abstract: A digital circuit for detecting a phase lock condition of a phase locked loop (PLL) circuit includes a pair of counters respectively receiving a digital signal produced by the PLL circuit, and a digital reference signal that is also received by the PLL circuit. A digital comparator is connected to the pair of counters for comparing count values contained therein at an end of a counting cycle, and for generating a first logic signal when the count values are the same and a second logic signal when the count values are different. A resettable memory receives the logic signals generated by the digital comparator and has a capacity sufficient to store a plurality of the logic signals resulting from successive comparisons.

Abstract: A delay circuit includes a first inverter connected to a supply voltage, and has an input for receiving an input signal. A delay regulating transistor is connected between the first inverter and a first voltage reference, and has a control terminal for receiving a biasing voltage. A capacitor is connected between an output of the first inverter and the first voltage reference. A second inverter is connected to the output of the first inverter for outputting a delayed output signal. An auxiliary current path is in parallel to the delay regulating transistor for allowing a portion of a discharge current from the capacitor to flow therethrough. The portion of the discharge current is proportional to the supply voltage. The auxiliary current path includes a diode connected to the first inverter, and a second transistor connected between the diode and the first voltage reference. The second transistor has a control terminal for receiving the biasing voltage.

Abstract: A substrate potential limiting device for an integrated circuit that includes a semiconductor substrate is provided. The device includes at least one unidirectional element connected between a substrate contact on the semiconductor substrate and a reference potential. The unidirectional element may be a bipolar transistor. The bipolar transistor includes a base and a collector connected to the at least one substrate contact and an emitter connected to the reference potential.