Abstract: The difference between the Vgs voltages of first and second MOS transistors of an integrated circuit due to variations in the production process and/or to variations of other parameters is compensated by a compensation circuit. The compensation circuit includes third and fourth MOS transistors that are the same type as the first and second transistors. These transistors are all formed in the same integrated circuit. The compensation circuit includes a bias circuit for biasing the third and fourth transistors, and a measurement circuit for measuring the difference between the Vgs voltages of the third and fourth transistors. The compensation circuit further includes a current compensation circuit for generating a compensation current that is a function of the difference measured, and a modification circuit for modifying the biasing of the first and second MOS transistor using the compensation current.

Abstract: Described herein is a nonvolatile memory comprising an input pin receiving an external clock signal supplied by a user; an input buffer receiving the external clock signal and supplying an intermediate clock signal delayed with respect to the external clock signal; and a delay locked loop receiving the intermediate clock signal and supplying an internal clock signal distributed within the nonvolatile memory and substantially in phase with the external clock signal.

Abstract: A neuro-fuzzy filter device that implements a moving-average filtering technique in which the weights for final reconstruction of the signal are calculated in a neuro-fuzzy network according to specific fuzzy rules. The fuzzy rules operate on three signal features for each input sample. The signal features are correlated to the position of the sample in the considered sample window, to the difference between a sample and the sample at the center of the window, and to the difference between a sample and the average of the samples in the window. The filter device for the analysis of a voice signal includes a bank of neuro-fuzzy filters. The signal is split into a number of sub-bands, according to wavelet theory, using a bank of analysis filters including a pair of FIR QMFs and a pair of downsamplers; each sub-band signal is filtered by a neuro-fuzzy filter, and then the various sub-bands are reconstructed by a bank of synthesis filters including a pair of upsamplers, a pair of FIR QMFs, and an adder node.

Abstract: An architecture for a pipeline processor circuit, preferably of the VLIW type, comprises a plurality of stages and a network of forwarding paths which connect pairs of said stages, as well as a register file for operand write-back. An optimization-of-power-consumption function is provided via inhibition of writing and subsequent readings in said register file of operands retrievable from said forwarding network on account of their reduced liveness length.

Abstract: The method is for reading a capacitive sensor and may be implemented by a circuit for biasing and reading capacitances that includes circuits for selecting a column line and a row line, and a charge amplifier producing an output voltage representing the capacitance of the selected capacitor intercepted by the selected column and row lines. The method includes preliminarily resetting the output voltage of the charge amplifier, connecting all the deselected row and column plates of the array to a reference voltage and connecting a feedback capacitor and the selected capacitor to an inverting input of the amplifier, applying a step voltage on the capacitor that is connected to the inverting input of the amplifier, and reading the output voltage at steady-state.

Abstract: A device for detecting the pressure exerted at different points of a flexible and/or pliable object that may assume different shapes, includes a plurality of capacitive pressure sensors and at least a system for biasing and reading the capacitance of the sensors. The requirements of flexibility or pliability are satisfied by capacitive pressure sensors formed by two orthogonal sets of parallel or substantially parallel electrodes spaced, at least at each crossing between an electrode of one set and an electrode of the other set, by an elastically compressible dielectric, forming an array of pressure sensing pixel capacitors. The system for biasing and reading the capacitance includes column plate electrode selection circuits and row plate electrode selection circuits and a logic circuit for sequentially scanning the pixel capacitors and outputting pixel values of the pressure for reconstructing a distribution map of the pressure over the area of the array.

Abstract: A byte-switch structure for electrically erasable and programmable non-volatile memories, includes a MOS transistor having a drain electrode coupled to a respective metal control gate line, a source electrode coupled to a respective polysilicon byte control line which is connected to control gate electrodes of all the memory cells of a same memory byte or word and is formed in an upper polysilicon layer, and a gate electrode coupled to a respective word line. The source and drain electrodes of the MOS transistor are respectively a first and a second doped regions of a first conductivity type formed in a semiconductor layer of a second conductivity type at opposite sides of the respective word line.

Abstract: A simplified non-DSCP process for the definition of the tunnel area in nonvolatile memory cells with semi-conductor floating gates is presented. The memory cells are non-aligned and are incorporated in a matrix of cells and have associated control circuitry. In additional, to each cell a selection transistor is associated. The process includes at least the following phases: growth or deposition of a dielectric layer of gate of the sensing transistor and of the cells; tunnel mask for defining the area of tunnel; cleaning etching of the dielectric layer of gate in the area of tunnel up to the surface of the semiconductor; and growth of tunnel oxide. Advantageously, the tunnel mask is extended above the region occupied by the selection transistor.

Abstract: A method for digital-to-analog conversion of a digital input code into a first output analog signal and a second output analog signal to be supplied to a first terminal and a second terminal, respectively, of an audio load, the conversion being performed by means of a DAC with N-level balanced output, the conversion method includes using N/2 positive generator elements supplying respective positive elementary contributions which are nominally equal to one another, and N/2 negative generator elements supplying respective negative elementary contributions which are nominally equal to one another and, in absolute value, equal to the positive elementary contributions; attributing the same progressive addresses to the positive generator elements and to the negative generator elements; defining a first index for the positive input codes and a second index for the negative input codes; and, in the presence of an input code at the input of the DAC, selecting between the first index and the second index, the index cor

Abstract: A process for connecting two bodies forming parts of an electromechanical, fluid and optical microsystem, wherein a welding region is formed on a first body; an electrically conductive region and a spacing region are formed on a second body; the spacing region extends near the electrically conductive region and has a second height smaller than said first height. One of the first and second bodies is turned upside down on the other, and the two bodies are welded together by causing the electrically conductive region to melt so that it adheres to the welding region and collapses until its height becomes equal to that of the spacing region. Thereby it is possible to seal active parts or micromechanical structures with respect to the outside world, self-align the two bodies during bonding, obtain an electrical connection between the two bodies, and optically align two optical structures formed on the two bodies.

Abstract: An integrated power device having a power transistor made up of a first diode and a second diode that are connected together in series between a collector region and emitter-contact region of the power transistor to define a common intermediate node, a control circuit including a high-voltage region bonded on the emitter-contact region (14) by means of an adhesive layer, and biasing circuit connected between the common intermediate node and the high-voltage region. The biasing circuit including a contact pad electrically connected to the common intermediate node, an electrical connection region that is in electrical contact with the high-voltage region (30), and a wire having a first end soldered on the contact pad and a second end soldered on said electrical connection region.

Abstract: Described herein is a method for storing a datum in a first and a second memory cells of a nonvolatile memory. The storage method envisages programming the first and second memory cells in a differential way, by setting a first threshold voltage in the first memory cell and a second threshold voltage different from the first threshold voltage in the second memory cell, the difference between the threshold voltages of the two memory cells representing a datum stored in the memory cells themselves.

Abstract: A switched capacitor low-pass filter incorporates a plurality of integrator stages cascade connected together. The filter includes at least one stage that includes a circuit device for cancelling out glitch pulses. This device is a deglitching circuit provided within the filter. Preferably, each stage in the filter is formed of a deglitching device which acts as a smoothing integrator.

Abstract: A word recognition device uses an associative memory to store a plurality of coded words in such a way that a weight is associated with each character of the alphabet of the stored words, wherein equal weights correspond to equal characters. To perform the recognition, a dictionary of words is first chosen; this is stored in the associative memory according to a pre-determined code; a string of characters which correspond to a word to be recognized is received; a sequence of weights corresponding to the string of characters received is supplied to the associative memory; the distance between the word to be recognized and at least some of the stored words is calculated in parallel as the sum of the difference between the weights of each character of the word to be recognized and the weights of each character of the stored words; the minimum distance is identified; and the word stored in the associative memory having the minimum distance is stored.

Abstract: The integrated circuit device has a vertical conduction structure in which a region, which contains the base of a bipolar transistor, has zones having different concentrations. The concentrations are lower where the flow of charges is more intense and higher elsewhere. A high gain of the bipolar transistor and a low resistance of the electronic switch in conduction are thus obtained.

Abstract: The device is constituted by an N+ substrate, by an N− layer on the substrate, by a metal contact for a collector, by a buried P− base region, by a P+ base contact and insulation region within which an insulated N region is defined, by a metal contact on the base contact region for a base, by an N+ emitter region buried in the insulated region and forming a pn junction with the buried base region, by a P+ body region in the insulated region, by an N+ source region in the P+ region, by a metal contact for a source, and by a gate electrode. In order to achieve a low resistance Ron, the P+ body region extends as far as the buried N+ emitter region and an additional N+ region is provided within the body region and constitutes a drain region, defining, with the source region, the channel of a lateral MOSFET transistor.

Abstract: An electrically alterable semiconductor memory includes at least two memory sectors the content of which is individually alterable, and a control circuit for controlling operations of electrical alteration of the content of the memory, permitting the selective execution of an operation of electrical alteration of the content of one of the memory sectors with the possibility of suspending the execution to permit read access to the other of the memory sectors. The control circuit is also capable of permitting, during the suspension, an operation of burst mode or page mode reading of the content of the other memory sector.

Abstract: The selection/deselection circuit is for non-volatile memory word lines having a decoding line connected between a supply voltage and ground, and including a series of decoding transistors of the same conductivity controlled by respective selection signals and at least a load transistor whose conductivity is opposite to the conductivity of the decoding transistors in series with the series of transistors and biased by a control voltage. The load transistor produces an activating or deactivating voltage of a memory word line, and a circuit for controlling the load transistor is provided. Such an auxiliary control circuit includes a sensing element in series with the decoding transistors and the load transistor for producing a sensing signal switching between a first value when only one memory line is actually selected and a second value when multiple memory word lines appear to be simultaneously selected.

Abstract: A switched mode power supply having a first circuit provided with a primary winding of a transformer to which a pulse voltage is applied, a second circuit having a secondary winding of the transformer, a reactor provided with a magnetic core and which has a terminal connected to a terminal of the secondary winding, at least one filter provided with input and output terminals and a first diode connected in parallel to the input terminals of the filter is shown. The other terminal of the reactor is connected to a terminal of the first diode. The power supply includes a second diode that has a first terminal connected to the other terminal of the first diode and a second terminal connected to the other terminal of the secondary winding and a control circuit coupled to an output terminal of the filter and to the other terminal of the secondary winding. The control circuit generates a current able to reset the magnetic core of the reactor.

Abstract: A method of driving an inductive load connected to an output of a power stage includes comparing a signal representative of an instantaneous value of current flowing through the inductive load with upper and lower thresholds during a switching cycle. The method also includes alternately performing a magnetization phase during which current is forced through the inductive load, and a demagnetization phase during which a load inductance of the inductive load discharges through at least one of a slow recirculation discharge current path and a fast recirculation discharge current path. Switching is performed between the slow and fast recirculation discharge current paths during each switching cycle as a function of the comparison for reducing a ripple on an output signal from the power stage.