Abstract: The non volatile memory device integrates, in one and the same chip, the array of memory cells, a voltage regulator which supplies a regulated operating voltage to a selected word line, and a short circuit detecting circuit. The short circuit detecting circuit detects the output voltage of the voltage regulator, which is correlated to the current for biasing the cells of the word line selected. Once settled to the steady state condition, the output current assumes one first value in the absence of short circuits, and one second value in the presence of a short circuit between the word line selected and one or more adjacent word lines. The short circuit detecting circuit compares the output current of the voltage regulator with a reference value and generates at output a short circuit digital signal which indicates the presence or otherwise of a short circuit.

Abstract: The step-up circuit has first and second input terminals for connection to a battery, first and second output terminals for connection to an electronic device to be fed by a DC/DC converter having a first and second input terminals connected respectively to the first and second input terminals of the step-up circuit. The second output terminal of the step-up circuit is connected to the second input terminal of the step-up circuit, one output terminal of the converter is connected to the first input terminal of the step-up circuit and the other output terminal of the converter is linked to the first output terminal of the step-up circuit, therefore, when operating, the output of the step-up circuit is the sum of the power of the battery and of the output of the converter. The step-up circuit is smaller, supplies the same output, is cheaper to produce and offers improved performance over the prior art.

Abstract: A method is provided for manufacturing masks of the EAPSM type used to produce integrated circuits. The method includes forming a shifter layer on a quartz layer, forming a chromium layer on the shifter layer, and forming a resist layer on the chromium layer. The resist layer is partially removed using a first exposure to a light source. The chromium layer is etched to form a plurality of openings, and the resist layer is removed. The method further includes etching the shifter layer at the plurality of openings. An additional layer of resist is formed on portions of the chromium layer, and exposed portions of the chromium layer are removed using a second exposure to the light source with a chromium removal window having dimensions smaller than, or equal to, dimensions of a step of a stepper unit used to transfer active devices of the EAPSM mask. The additional layer of resist is then removed.

Abstract: A nonvolatile semiconductor memory device structure having a matrix of memory cells in a semiconductor material layer. The memory cells are located at intersections of rows and columns of the matrix. Each memory cell includes a control gate electrode connected to one of the rows, a first electrode connected to one of the columns and a second electrode. The rows comprise polysilicon strips extending parallel to each other in a first direction, and the columns are formed by metal strips extending parallel to each other in a second direction orthogonal to the first direction. Short-circuit metal strips are coupled for short-circuiting the second electrodes of the memory cells. The columns and the short-circuit strips arc respectively formed in a first metal level and a second metal level superimposed on each other and electrically insulated by a dielectric layer.

Abstract: A low-consumption TTL-CMOS input buffer stage includes a chain of inverters cascade connected between an input receiving electric signals at a TTL logic level and an output reproducing electric signals at a CMOS logic level, and powered between a first or supply voltage reference and a second or ground reference. Advantageously, the first inverter in the chain includes a means of selecting the delivery path to the stage according to an activate signal for a low-consumption operation mode. In essence, the first inverter of the buffer has two signal paths: one for normal operation and the other for low consumption operation.

Abstract: A programmable logic array (PLA) includes at least one AND plane including an array of transistors arranged in rows and columns. The transistors belonging to a same column may be connected in series with each other. Two end conduction terminals of the series connected transistors may be coupled to a supply voltage rail and to a reference, respectively. The transistors of the first and last rows of the array may have their control terminals coupled to respective opposite enabling/disabling potentials. Except for the first and last rows, first, second, and third control lines are associated with each row of the array. Except for the first and last rows, each transistor of each row may have its control terminal connected to one of the three control lines associated with its row. The PLA may alternatively include at least one OR plane.

Abstract: A process for cutting a trench in a silicon monocrystal in areas defined by a mask comprises forming a mask that defines an etched area on the surface of a monocrystalline silicon wafer which is eventually covered by a thin layer of oxide. Next, ions are implanted with a kinetic energy and in a dose sufficient to amorphize the silicon down to a predefined depth within the defined area, while maintaining the temperature of the wafer sufficiently low to prevent relaxation of point defects produced in the silicon and to prevent diffusion of the implanted ions in the crystal lattice of the silicon adjacent to the amorphized region. Dislodgment and expulsion of the amorphized portion in correspondence with interface with the adjacent crystal lattice of the silicon is initiated by heating the implanted wafer.

Abstract: The present invention relates to a circuit device for protection against electrostatic discharge, and being immune to the latch-up phenomenon. The circuit device is of the integrated type in a portion of a semiconductor integrated circuit. The device includes an active limiting element and a resistor connected in series between a terminal of the active element connected to an input/output pin of the integrated circuit, and a terminal of a circuit to be protected. The active element is a bipolar transistor having a base terminal and an emitter-acting collector terminal connected together. The distributed resistor is formed in an emitter-acting collector region of the transistor which is diffused and elongated at the surface inside a base pocket of the transistor.

Abstract: A biasing device for biasing a memory cell having a substrate bias terminal associated therewith. The biasing device includes a first sub-threshold circuitry block adapted to supply an appropriate current during the device standby phase through a restore transistor connected between a supply voltage reference and the substrate bias terminal of the memory cell, and having a control terminal connected to a bias circuit, in turn connected between the supply voltage reference and a ground voltage reference to drive the restore transistor with a current of limited value.

Abstract: A method of synchronizing the start of sequential read cycles when reading data in a memory in a synchronous mode with sequential access uses the increment pulses as synchronization signals for the address counters of the memory cell array. Following each increment pulse, a dummy ATD pulse is generated. The dummy ATD pulse is undistinguishable from an ATD pulse generated upon detection of a switching of external address lines.

Abstract: A manufacturing process that includes, in succession: depositing a gate oxide layer on a silicon substrate defining a transistor area and a resistor area; depositing a multicrystal silicon layer on the gate oxide layer; removing selective portions of the multicrystal silicon layer to form a gate region over the transistor area and a protective region completely covering the resistor area; forming source and drain regions in the transistor area, laterally to the gate region; forming silicide regions on and in direct contact with the source and drain regions, the gate region and the protective region; removing selective portions of the protective region to form a delimitation ring; and implanting ionic dopants in the resistor area, inside the area defined by the protective ring, to form a lightly doped resistor which has no silicide regions directly on it.

Abstract: Method of manufacturing an edge structure for a high voltage semiconductor device, including a first step of forming a first semiconductor layer of a first conductivity type, a second step of forming a first mask over the top surface of the first semiconductor layer, a third step of removing portions of the first mask in order to form at least one opening in it, a fourth step of introducing dopant of a second conductivity type in the first semiconductor layer through the at least one opening, a fifth step of completely removing the first mask and of forming a second semiconductor layer of the first conductivity type over the first semiconductor layer, a sixth step of diffusing the dopant implanted in the first semiconductor layer in order to form a doped region of the second conductivity type in the first and second semiconductor layers.

Abstract: A method for testing memory cells, and in particular virgin memory cells, in a multilevel memory device having a plurality of memory cells.

Abstract: The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material.

Abstract: A method and apparatus to dynamically modify the internal compensation of a low drop out linear voltage regulator is presented. The process involves using zero mobile compensation; when the output pole of the voltage regulator moves, a compensating zero is moved toward higher frequencies. This compensation zero is used to compensate the effect of a second pole in the loop gain. The circuit includes an input stage having an error amplifier. The error amplifier includes a differential stage output coupled to an output terminal of the buffer stage. An output stage of the circuit includes an output transistor having a conduction terminal connected to an output terminal of the voltage regulator, and having a control terminal coupled to the output terminal of the buffer stage. Additionally, a variable compensation network is connected between the differential stage output and a voltage reference. This variable compensation network can include an RC circuit having a resistive transistor.

Abstract: The sensing circuits comparing the current flowing in the cell with a plurality of reference currents are not identical to each other but differently amplify the compared currents. In particular, the sensing circuit associated with the lowest reference current amplifies the cell current more than the other sensing circuits and to the respective reference current. The current dynamics is thereby increased and it is possible to keep the reading voltage low, since the inherent characteristic of the lowest reference current may be very close to or directly superimposed on that of the immediately preceding memory cell current distribution, retaining the possibility of discriminating between the different logic levels.

Abstract: A non-volatile memory device is organized with memory cells that are arranged by row and by column. The memory device includes a sector of matrix cells, row decoders and column decoders suitable to decode address signals and to activate respectively the rows or said columns, at least a sector of redundancy cells such that it is possible to substitute a row of the sector of matrix cells with a row of the sector of redundancy cells. The non-volatile memory device comprises a local column decoder for the matrix sector and a local column decoder for the redundancy sector. The local column decoders are controlled by external signals so that the row of the redundancy sector is activated simultaneously with the row of the matrix sector.

Abstract: A process for manufacturing electronic semiconductor integrated electronic memory devices having virtual ground and including at least a matrix of floating gate memory cells formed on a semiconductor substrate with a plurality of continuous bit lines extending across the substrate as discrete parallel strips begins with forming an oxide layer over the matrix region. Then, the semiconductor throughout is deposited with a stack structure which includes a first conductor layer, a first dielectric layer, and second conductor layer. Next, a second dielectric layer is formed. Floating gate regions are defined by photolithography using a mask of “POLY1 along a first predetermined direction”, and associated etching, to define, in the stack structure, a plurality of parallel openings. These openings are implanted to confer a predetermined conductivity on the bit line regions. Next, the parallel openings are filled with a photo-sensitive material to protect the matrix bit lines.

Abstract: Presented is a process for manufacturing virtual ground electronic memory devices integrated in a semiconductor having a conductivity of a first type and having at least one matrix of floating gate memory cells. In the matrix there are a number of continuous bit lines extending across the substrate as discrete parallel strips, and a number of word lines extending in a transverse direction to the bit lines. The method begins by forming gate regions of the memory cells to produce a number of continuous strips seperated by parallel openings. Then, a dopant is implanted to form, within the parallel openings, the bit lines with conductivity of a second type. Spacers are formed on sidewalls of the gate regions. Then a first layer of a transition metal is deposited into said parallel openings, and the transition metal layer is subjected to a thermal treatment for reacting it with semiconductor substract and forming a silicide layer over the bit lines.

Abstract: The components used in the method comprise a heat-dissipating base plate, one or more three-layer plates (the top layer consisting of copper plates and strips) and a one-piece frame designed to constitute the terminals. After the chips have been soldered onto the upper plates and connected to the strips, the inner ends of the frame are soldered to points of connection with the chips. This is followed by the encapsulation in resin and the shearing of the outer portions of the frame, which, during the process, serve to temporarily connect the terminals.