Abstract: The analog processor of this invention is programmable and capable of storing the processing coefficients in analog form. It comprises a storage section having at least one output, plural outputs in most cases, and being adapted to respectively generate programming signals on such outputs; the storage section is input a plurality of supply voltage signals and is operative to produce, in connection with information stored therein, one of the supply voltage signals on each of the outputs, it being understood that one voltage signal may be produced on several such outputs. Advantageously, the processor can also be programmed in a simple manner from circuits of the digital type if switches controlled by storage elements are used in the storage section.

Abstract: A redundancy architecture for a memory includes an array of memory cells divided into at least a pair of semi-arrays that are singularly addressable. Each semi-array is organized into rows and columns. The redundancy architecture includes a number of packets each including redundancy columns. The packets are divided into two subsets of packets. Each packet is addressable independently from the other by respective address circuits. Each packet also provides redundancy columns exclusively for a respective semi-array.

Abstract: An active precision termination of the type incorporated in a voltage regulator for feeding the lines of an external bus is presented. Each termination includes a matching impedance connected in series to a switch formed by a MOS transistor, including a cell formed by a plurality of circuit branches provided in parallel and coupled to a unique output terminal. Each branch includes an input coupled to the series of the impedance and of the switch and receiving a control voltage signal. The body terminal of each MOS transistor receives a corresponding control signal via an inverter, whereas the control terminal of each MOS transistor receives a corresponding control voltage signal.

Abstract: A transistor including an epitaxial layer with a first conductivity type, a base buried region with a second conductivity type, and a sinker base region with the second conductivity type which extends from a main surface of the transistor to the base buried region, and delimits, together with the base buried region, emitter fingers in the epitaxial layer. The transistor further includes an emitter buried region with the first conductivity type and a doping level which is higher than that of the epitaxial layer. The emitter buried region is embedded in the epitaxial layer in a position adjacent to the base buried region. A sinker emitter region having the first conductivity type and a doping level which is higher than that of the epitaxial layer and extends from the main surface to the emitter buried region inside the emitter fingers.

Abstract: A robust communication system for transmitting through a noisy environment includes a signal source for providing discrete signals, a chaotic modulator for modulating the discrete signals, and an incoherent discriminator or receiver for receiving the modulated signals. The incoherent discriminator includes a high-pass filter for removing the lowest frequency harmonics of the received signals, a rectifier for providing an absolute value of the received signals, a low-pass filter and a comparator after the low-pass filter.

Abstract: A circuit structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element that has a bottom and a top electrode. The MOS device has conduction terminals formed in the semiconductor layer, as well as a control terminal covered with an overlying insulating layer of unreflowed oxide. The capacitor element is formed on the unreflowed oxide layer.

Abstract: A process for the manufacture of a non-volatile memory with memory cells arranged in word lines and columns in a matrix structure, with source lines extending parallel and intercalate to said lines, said source lines formed by active regions intercalated to field oxide zones, said process comprising steps for the definition of active areas of said columns of said matrix of non-volatile memory cells and the definition of said field oxide zones, subsequent steps for the definition of the lines of said matrix of non-volatile memory cells, and a following step for the definition of said source lines.

Abstract: A method for fabricating a silicon-on-insulator (SOI) wafer that includes a monocrystalline silicon substrate with a doped region buried therein is provided. The method includes forming a plurality of trench-like openings extending from a surface of the substrate to the doped buried region, and selectively etching through the plurality of trench-like openings to change the doped buried region into a porous silicon region. The porous silicon region is oxidized to obtain an insulating region for the SOI wafer.

Abstract: A data output buffer includes an output node, and a first stage connected to the output node for providing a first control signal for precharging the output node to an intermediate voltage with respect to a voltage for switching the output node from a current logic state to a different logic state. A second stage is connected to the first stage and to the output buffer. The first and second stages are responsive to a second control signal for enabling output of new data. A precharge logic circuit precharges the output node to the intermediate voltage as a function of data last output, and as a function of first and second reset signals until a rising and falling edge of the data last output respectively crosses the intermediate voltage.

Abstract: A device controller controls access to a device, such as a television, having a power input for receiving power and a data input for receiving control data. When in standby mode, the device controller disconnects the device from a power source, such as the AC mains of the building in which the device is situated. As a result, in standby mode only the device controller is powered, which uses much less power than prior art devices in standby mode. The device controller includes an input device structured to provide control data based on control instructions received from a user, a power switch coupled between a power source and the device power input, and a data coupler coupled to the device data input and structured to convert electrical data into non-electrical data and back to the electrical data for delivery to the device data input.

Abstract: A non-volatile memory device organized with memory cells arranged by rows and columns in a matrix structure comprising source lines for memory cell groups. A switch is set between at least two rows or columns or source lines, which has two no pilotable terminals connected respectively to each one of the two rows or columns or source lines and a pilotable terminal connected to a logic circuitry. The switch allows a precharge of one of the two rows or columns or source lines by capacitive means associated to a each one of the two rows or columns or source lines after the other of the two rows or columns or source lines is connected to a higher voltage than that of said one of the two rows or columns or source lines.

Abstract: A method for the in-writing verification of the threshold value of the multilevel cells suitable to memorize n bits each, that provides for the utilization of a sense amplifier containing a respective successive approximation register. An output signal of a comparison circuit provides for the loading of the datum to be programmed in the cell being selected, after which a programming pulse is applied and the comparison between the reference current corresponding to said datum and the current that flows in the cell is carried out. The application of the programming pulse and the performance of the comparison are then repeated until it is verified that the current of the cell is smaller than the reference current.

Abstract: An electronic device is formed on a chip of semiconductor material covered by a layer of insulating material. Metal interconnection elements form, on the insulating layer, connection pads to which a soldering material is applied. To permit good heat dissipation, the device has a metal plate partially incorporated in the insulating layer and having a surface which is coplanar with the pads and to which soldering material is applied. The electronic device is secured to a mounting substrate having a corresponding metal plate.

Abstract: A method of and system for providing user input to a computer captures a first finger position image at a first time and a second finger position image at a second time. The first and second finger position images each comprise a plurality of numerical gray scale values equal to or greater than zero. The system then subtracts the first finger position image from the second finger position image to obtain a composite image. The composite image has a first region comprising numerical values less than zero and a second region comprising numerical values greater than zero. The system provides X-Y input to the computer based upon the relative positions of first and second regions. The system further provides Z input to the computer based upon the relative sizes of said first and second regions.

Abstract: A protection circuit of a diagnostic output line (K-line) of a control unit for protection of the control unit in the event of a ground disconnection or of a “below ground” condition is provided. The diagnostic output line includes a first interface DMOS transistor with a source connected to ground and a drain coupled to the diagnostic output line through a second DMOS transistor with a source connected to the output line and a drain connected to the source of the first DMOS transistor. The protection circuit also includes a comparator for the voltage of the diagnostic output line with the potential of the ground node, and a two-input logic gate, whose output controls a current generator forcing a current, limited by a resistor, on the diagnostic output line.

Abstract: A switching output power stage, including a power switching device for the supply line and a complementary power switching device for the ground rail driven in phase opposition by a pulse width modulated (PWM) drive signal, is provided with sensors detecting a substantial turn-off state of each of the two power switching devices and generating a pair of logic signals. A combinatory logic circuit combines the drive signal and the pair of logic signals and generates a pair of driving signals of opposite phase for the respective power switching devices. The switching to a turn-on state of any of the two power devices is enabled upon verifying a substantially attained turn-off state by the device complementary to the device commanded to turn-on, irrespective of the process spread and of changes of temperature load conditions and of configuration of a plurality of output stages of a multichannel amplifier.

Abstract: A bias circuit for read amplifier circuits for memories includes at least one first circuit branch formed by a first pair of MOS transistors connected between a supply voltage and ground. The first pair of MOS transistors includes a P-channel diode connected transistor and an N-channel transistor connected in series, with an enable transistor interposed therebetween. The first circuit branch drives a capacitive load for coupling to the supply voltage. The bias circuit further includes reference current amplifier circuit branches for amplifying a reference current which flows in the first circuit branch for charging the capacitive load. A circuit portion, which controls the charging current of the capacitive load, includes a feedback loop between the reference current amplifier circuit branches and the capacitive load.

Abstract: A monolithically integrated selector for electrically programmable memory cell devices can be switched at an output terminal (OUT) between a high voltage (HV) and a low voltage (LV). It comprises a leg (N2, N1) of fast ground discharge (GND) from the output terminal, a discharge control leg (P1, N3, N4) driving the selector switching through a phase generator (PHG).

Abstract: The high-voltage bidirectional switch includes a controlled transistor having a first terminal and a second terminal set, respectively, at a first potential and at a second potential. The controlled transistor moreover includes a control terminal connected to a control block, which is in turn connected to a precharge block The controlled transistor has its bulk region connected to a biasing block which is in turn connected both to the precharge block and to the second terminal of the controlled transistor. The control block and the biasing block are moreover connected to a signal-generator block connected to a control unit.

Abstract: A voltage level shifter and an associated level shifting method for shifting from a low voltage input signal to a high voltage output signal are discussed. The level shifter includes a voltage shifting stage having first and second control input nodes and an output node at which the output signal is produced based on control signals received at the control input nodes. The level shifter also includes first and second input inverters coupled in series between the input node and the first control input node; and a third input inverter coupled between the input node and the second control input node. The second inverter can include complementary first and second transistors each with control terminals coupled to an output of the first inverter. The first transistor has a first terminal coupled to the input node and is structured to pass the input signal to the first control input node based on a logic value of a signal output by the first inverter.