Abstract: A method for forming and bonding a metal bump on a metal pad of an integrated circuit and successively stamping a vertex of the bonded metal bump is performed using the same capillary tool. The dielectric and refractory tip of the capillary tool ends with a flat surface forming a sharp edge adjacent a concave mouth formed therein. A preformed metal ball held in the concave mouth is bonded to the metal pad of the integrated circuit. The method further includes the step of retracting the capillary tool from the bonded metal bump while allowing free movement of the capillary tool relative to the metal wire passing through an axial conduit of the capillary tool. Relative movement of the metal wire is blocked by clamping the metal wire as soon as the capillary tool is pulled off the bonded metal bump. The capillary tool is then laterally shifted for breaking off the metal wire.

Abstract: An electronic memory circuit comprises a matrix of EEPROM memory cells. Each memory cell includes a MOS floating gate transistor and a selection transistor. The matrix includes a plurality of rows and columns, with each row being provided with a word line and each column comprising a bit line organized in line groups so as to group the matrix cells in bytes, each of which has an associated control gate line. A pair of cells have a common source region, and each cell symmetrically provided with respect to this common source region has a common control gate region.

Abstract: Circuit for the regulation of the word line voltage in a memory, including a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more word lines of the memory when said one or more word lines are being selected, and charge accumulation means that are selectively connectable with the output of the voltage regulator and suitable to accumulate a compensation charge for a voltage drop that takes place on said regulated voltage upon the selection of said one or more word lines of the memory.

Abstract: A protection circuit is disclosed for a bipolar power transistor for preventing the operating point thereof from leaving a useful operating area. The protection circuit includes a sense resistor connected between an input supply voltage and a collector of the bipolar power transistor; a first branch circuit, including a first diode connected to the collector of the bipolar power transistor and a first current source connected between a common output node and the first diode; a second branch circuit, including a second diode and a second current source connected between the second diode and the common output node; and a third branch circuit. A short-circuit current level of the bipolar power transistor at relatively low voltage levels of the input supply voltage is based upon current levels for the first current source and the second current source and a resistance value of the sense resistor connected to the bipolar power transistor.

Abstract: A method for storing n bytes in multi-level non-volatile memory cells, including writing and reading of said n bytes. Writing includes the following steps: (a) decomposing each one of such n bytes into eight bits, (b) storing each one of such eight bits into a respective one of such multi-level non-volatile memory cells by utilizing a multi-level technology. Reading includes the following steps: (c) reading contemporaneously each one of such eight bits which belong to each one of said n bytes by sense amplifiers each connected to each one of such multi-level non-volatile memory cells, (d) assembling such eight bits previously read to form each one of such initial n bytes.

Abstract: Array of electrically programmable non-volatile memory cells, each cell comprising a stacked-gate MOS transistor having a lower gate electrode, an upper gate electrode coupled to a row of the array, a first electrode associated with a column of the array and a second electrode separated from the first electrode by a channel region underlying said lower gate electrode, the first electrode, the second electrode and the channel region being formed in a layer of semiconductor material of a first conductivity type and having a second conductivity type, comprising at least one ROM memory cell which identically to the electrically programmable non-volatile memory cells comprises a stacked-gate MOS transistor and is associated with a respective row and a respective column of the array, the ROM cell including means for allowing or not allowing the electrical separation between said respective column and the second electrode of the ROM cell, if the ROM cell must store a first logic state or, respectively, a second logi

Abstract: A circuit for the regulation of the word line voltage in a memory, comprising a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more word lines of the memory when the one or more word lines are being selected. The circuit includes a voltage boosting circuit that is coupled to the output of said voltage regulator and that can be activated upon the selection of one or more memory word lines in order to boost the regulated voltage upon the selection of the one or more memory word lines.

Abstract: A microactuator comprises an outer stator and an inner rotor electrostatically coupled to a stator. The rotor comprises a suspended mass with a substantially circular shape, and a plurality of mobile arms extending radially towards the exterior, starting from the suspended mass. The stator has a plurality of pairs of fixed arms extending radially to the suspended mass, a respective mobile arm being arranged between each pair of fixed arms. The fixed arms are divided into fixed drive arms connected to a drive stage for actuating the microactuator, and into fixed measure arms connected to a measure stage, and define a capacitive uncoupling structure.

Abstract: A semiconductor memory cell having a word line, a bit line, a precharge line, an access transistor, and first and second cross-coupled inverters. The first inverter includes a first P-channel transistor and a first N-channel transistor, and the second inverter includes a second P-channel transistor and a second N-channel transistor. The access transistor selectively couples the bit line to an output of the first or second inverter, and one terminal of the first N-channel transistor is connected to the precharge line. In a preferred embodiment, a control circuit is provided that, during a writing operation, supplies data to be written to the memory cell to the bit line, supplies a pulse signal to the precharge line, and activates the word line. A method of writing data to a semiconductor memory cell that is coupled to a word line and single bit line is also provided.

Abstract: A low-cost semiconductor user input device for controlling the position of a pointer on a display includes a small array of composite sensors. Each composite sensor of the array is adapted to detect movement of a fingerprint feature. The user input device moves the pointer based upon the net movement detected by the composite sensors of the array.

Abstract: The anti-pop circuit includes a unity gain buffer with an input coupled to the source of the reference voltage and an output coupled to the input of the amplifier to accelerate the charging of the input coupling capacitor of the amplifier at every turn-on. The capacitor-charging buffer is automatically disabled before the turning-on of the amplifier. The charging buffer may be enabled at start up by generating an impulse of a pre-established duration at the turn-on instant by a monostable circuit or by disabling it upon verifying the decaying to zero of the charging of current of the input coupling capacitor. The circuit eliminates the popping noise at the turn-on without an excessive delay of the turning-on of the amplifier.

Abstract: A circuit controls switching of a load between two supply terminals by a device in an emitter-switching configuration formed by a high-voltage bipolar power transistor and a low-voltage switch element. The bipolar power transistor has a collector connected to the load. The switch element has a first terminal connected to the emitter of the bipolar power transistor, a second terminal connected to ground, and a control terminal connected to a control terminal of the circuit. The circuit has a biasing circuit connected to a base terminal of the bipolar power transistor. To ensure that the bipolar power transistor operates in the saturation region throughout the period of conduction, even with a sinusoidal driving voltage, the biasing circuit includes a capacitive device and a charging circuit for charging the capacitive device to bias the base of the bipolar power transistor.

Abstract: An intelligent suction device, particularly for vacuum cleaners and the like, includes a fuzzy-logic controller for controlling the motor of a fan or turbine. The suction pressure is detected by at least one pressure sensor which feeds back its measurement, in a closed loop, to the controller.

Abstract: Presented is a circuit device for driving an a.c. electric load, incorporating a rectifying bridge that has a first input connected to one terminal of the electric load and a second input connected to an outlet of an a.c. main supply. The rectifying bridge has output terminals connected to a power switch which is controlled by an electric signal. The circuit device has a circuit loop-back link connected in parallel to the electric load, and a second circuit loop-back link connected in parallel to the electric load. The first and second links are alternately activated by the positive and negative half-waves of the main supply when the switch is in its “off” state.

Abstract: The driving capability of a selection transistor is increased by an N-type implant at the source and drain regions of the selection transistor itself. This implant is conveniently made at the end of the self-aligned etching, using the same self-aligned etching mask defining the control gate regions and the floating gate regions of memory elements, keeping the circuitry area covered by a circuitry mask.

Abstract: A semiconductor non-volatile memory device that includes memory cells and selection transistors. The memory cells each include a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, and each of the floating gate transistors is serially coupled to one of the selection transistors. A contact to the control gate is located above the active area. In a preferred embodiment, the contact is substantially aligned with a central portion of the active area. A method for manufacturing a non-volatile memory device on a semiconductor substrate is also provided. According to the method, a poly1 layer is deposited, an interpoly dielectric layer is deposited above the poly1 layer, and a poly2 layer is deposited above the interpoly dielectric layer. A mask is provided to define the control gate, and a Self-Aligned poly2/interpoly/poly1 stack etching is used to define a gate stack structure that includes the control gate and the floating gate.

Abstract: A process for manufacturing a MOS transistor and especially a MOS transistor used for non-volatile memory cells is presented. At the start of the manufacturing, a semiconductor substrate having a first type of conductivity is covered by a gate oxide layer. A gate electrode is formed over the gate oxide layer, which is a stacked gate when the MOS transistor is used in a non-volatile memory. Covering the gate electrode is a covering oxide that is formed over the gate oxide layer, the gate electrode, and around the gate electrode. Next, a dopant of a second type of conductivity is implanted to provide implant regions adjacent to the gate electrode. Subjecting the semiconductor to thermal treatments allows the implanted regions to diffuse into the semiconductor substrate under the gate electrode and form a gradual junction drain and source region of the MOS transistor.

Abstract: The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors having source and drain terminals which are coupled together and to an injection node, and at least one corresponding pair of generators of substantially step-like voltage signals having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors. The signal generators are such that the initial value of a first of the signals is substantially the equal of the final value of a second of the signals, and that the final value of the first signal is substantially the equal of the initial value of the second signal.

Abstract: A manufacturing method having the steps of: depositing an upper layer of polycrystalline silicon; defining the upper layer, obtaining LV gate regions of low voltage transistors and undefined portions; forming LV source and drain regions laterally to the LV gate regions; forming a silicide layer on the LV source and drain regions, on the LV gate regions, and on the undefined portions; defining salicided HV gate regions of high voltage transistors; and forming HV source and drain regions not directly overlaid by silicide portions.

Abstract: A process of manufacturing cross-point matrix memory devices which have floating gate memory cells having the source channel self-aligned to the bit line and the field oxide is disclosed. The process includes the steps of growing a thin layer of tunnel oxide on the matrix region; depositing a stack structure comprising a first conductive layer, an intermediate dielectric layer, and a second conductive layer; photolithographing with a Polyl mask to define a plurality of parallel floating gate regions in the stack structure; self-aligned etching of the stack structure, above the active areas, to define continuous bit lines; and implanting, to confer predetermined conductivity on the active areas . Advantageously, the self-aligned cascade etching step for removing parallel strips from multiple layers, down to the active areas of the substrate, is discontinued before the field oxide is removed, and the implantation step is carried out in the presence of field oxide over the source active areas.