Patents Assigned to STMicroelectronics SA.A.
  • ARBITRATION DEVICE
    Publication number: 20200225986
    Abstract: Requests are received by a routing circuit. A plurality of first round-robin arbitration circuits are coupled to the routing circuit. There are as many first round-robin arbitration circuits as there are possible priority levels for the requests. The routing circuit operates to transmit each received request to a number of first round-robin arbitration circuits determined according to the priority level of the request. A second round-robin arbitration circuit has inputs respectively connected to the outputs of the first round-robin arbitration circuits.
    Type: Application
    Filed: January 10, 2020
    Publication date: July 16, 2020
    Applicants: STMicroelectronics SA, STMicroelectronics (Grenoble 2) SAS
    Inventors: Bruno DENIS, Christophe TABA
  • Transmission line with device for limiting losses through impedance mismatch
    Patent number: 10715113
    Abstract: An attenuator having an impedance that is controllable by a first setpoint signal is coupled to a transmission line. A matching circuit having an impedance that is controllable by a second setpoint signal is also coupled to the transmission line. A transformer circuit block also coupled to the transmission line has a complex impedance. A control circuit sets the first and second setpoint signals so as to control a conjugate impedance relationship between the variable impedances presented by the attenuator and matching circuit relative to the complex impedance of the transformer circuit.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: July 14, 2020
    Assignee: STMicroelectronics SA
    Inventors: Bruno Grelaud, Sebastien Pruvost
  • ELECTRONIC DEVICE FORMING A DIGITAL-TO-ANALOG CONVERTER AND A MIXER
    Publication number: 20200212927
    Abstract: An acquisition stage receives a digital input signal and generates therefrom a first digital signal and a second digital signal complementary thereto. First and second processing stages receive the first and second digital signals and generate therefrom first and second analog signals in time with first and second complementary clock signals. An output stage generates an internal clock signal equivalent to one of: the first clock signal phase shifted by a duration of a transient occurring during a period of the first clock signal, or the second clock signal phase shifted by a duration of a transient occurring during a period of the second clock signal. The output stage produces an analog output signal equal to the first analog signal when the internal clock signal is at a first logic level, and equal to the second analog signal when the internal clock signal is at a second logic level.
    Type: Application
    Filed: December 10, 2019
    Publication date: July 2, 2020
    Applicants: STMicroelectronics SA, STMicroelectronics (Alps) SAS
    Inventors: Stephane LE TUAL, Jean-Pierre BLANC, David DUPERRAY
  • Method of controlling the adaptation of an antenna to a transmission path, and corresponding device
    Patent number: 10686475
    Abstract: A method is provided for controlling the matching of an antenna to a transmission path. The transmission path includes an amplifier stage coupled at an input or at an output to the antenna and to a resistive load. The method includes performing a checking phase by measuring a first current temperature at or in proximity of the antenna and a second current temperature at or in proximity of the resistive load, triggering a matching of the impedance seen at the input or at the output of the amplifier stage in the presence of a first condition involving the first and second current temperatures, and then stopping the matching of the impedance in the presence of a second condition involving the second current temperature.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: June 16, 2020
    Assignee: STMicroelectronics SA
    Inventors: Vincent Knopik, Boris Moret, Eric Kerherve
  • Method for producing low-permittivity spacers
    Patent number: 10658197
    Abstract: There is provided a method for manufacturing a transistor from a stack including at least one gate pattern comprising at least one flank, the method including forming at least one gate spacer over at least the flank of the gate pattern; and reducing, after a step of exposure of the stack to a temperature greater than or equal to 600° C., of a dielectric permittivity of the at least one gate spacer, the reducing including at least one ion implantation in a portion at least of a thickness of the at least one gate spacer.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: May 19, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Nicolas Posseme, Maxime Garcia-Barros, Yves Morand
  • Integrated electronic device suitable for operation in variable-temperature environments
    Patent number: 10659034
    Abstract: An integrated electronic device includes a silicon-on-insulator (SOI) substrate. At least one MOS transistor is formed in and on the SOI substrate. The at least one MOS transistor has a gate region receiving a control voltage, a back gate receiving an adjustment voltage, a source/drain region having a resistive portion, a first terminal coupled to a first voltage (e.g., a reference voltage) and formed in the source/drain region and on a first side of the resistive portion, and a second terminal generating a voltage representative of a temperature of the integrated electronic device, the second terminal being formed in the source/drain region and on a second side of the resistive portion. Adjustment circuitry generates the adjustment voltage as having a value dependent on the control voltage and on the voltage generated by the second terminal.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: May 19, 2020
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Renan Lethiecq
  • Method for estimating an operating profile of an integrated circuit of a system-on-a-chip, and corresponding system-on-a-chip
    Patent number: 10634715
    Abstract: A method for determining a margin of use of an integrated circuit includes monitoring at least one sensor so as to determine at least one physical parameter representative of use of the integrated circuit, evaluating the at least one physical parameter to determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter, and calculating the margin of use for the integrated circuit from a comparison of the instantaneous state of aging with a presumed state of aging. If operation of the integrated circuit is outside the margin of use, at least one operating performance point of the integrated circuit is adjusted so as to bring operation of the integrated circuit back within the margin of use.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: April 28, 2020
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Vincent Huard, Chittoor Parthasarathy
  • FLIP-FLOP WITH A METAL PROGRAMMABLE INITIALIZATION LOGIC STATE
    Publication number: 20200112301
    Abstract: A standard cell layout for a data storage circuit includes a latch and an initialization circuit. Metallization levels over the standard cell layout support circuit interconnections. At least one metallization level is provided for metal programming of an initialization configuration of the data storage circuit. The at least one metallization level may have: a first wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in reset device (assertion of an initialization signal causing the data storage circuit data output to be reset), or a second wiring layout for interconnecting the initialization circuit to the latch for configuration programming of the data storage circuit as an initialization in set device (assertion of the initialization signal causing the data storage circuit data output to be set).
    Type: Application
    Filed: October 16, 2019
    Publication date: April 9, 2020
    Applicant: STMicroelectronics SA
    Inventors: Sylvain ENGELS, Alain AURAND, Etienne MAURIN
  • BIPOAR TRANSISTOR
    Publication number: 20200111889
    Abstract: A bipolar transistor includes a collector. The collector is produced by a process wherein a first substantially homogeneously doped layer is formed at the bottom of a cavity. A second gradually doped layer is then formed by diffusion of dopants of the first substantially homogeneously doped layer.
    Type: Application
    Filed: October 2, 2019
    Publication date: April 9, 2020
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Alexis GAUTHIER, Pascal CHEVALIER
  • BIPOLAR TRANSISTOR
    Publication number: 20200111890
    Abstract: A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.
    Type: Application
    Filed: October 2, 2019
    Publication date: April 9, 2020
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Alexis GAUTHIER, Pascal CHEVALIER
  • Method for protecting a program code, corresponding system and processor
    Patent number: 10613993
    Abstract: Program code intended to be copied into the cache memory of a microprocessor is transferred encrypted between the random-access memory and the processor, and the decryption is carried out at the level of the cache memory. A checksum may be inserted into the cache lines in order to allow integrity verification, and this checksum is then replaced with a specific instruction before delivery of an instruction word to the central unit of the microprocessor.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: April 7, 2020
    Assignee: STMICROELECTRONICS SA
    Inventor: Bruno Fel
  • Electrostatic discharge (ESD) protection for a high side driver circuit
    Patent number: 10607949
    Abstract: Electrostatic discharge (ESD) protection is provided by a circuit including a resistor having a first terminal and a second terminal, a zener diode having a cathode terminal directly connected to said first terminal and an anode terminal directly connected to a third terminal, and a clamp diode having a cathode terminal directly connected to said second terminal and an anode terminal directly connected to said third terminal.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: March 31, 2020
    Assignees: STMicroelectronics (Alps) SAS, STMicroelectronics SA
    Inventors: Yves Mazoyer, Philippe Galy, Philippe Sirito-Olivier
  • ELECTRONIC DEVICE PROVIDING A TEMPERATURE SENSOR OR A CURRENT SOURCE DELIVERING A TEMPERATURE-INDEPENDENT CURRENT
    Publication number: 20200097036
    Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal operates to impose the drain-source current of the first transistor.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 26, 2020
    Applicant: STMicroelectronics SA
    Inventors: Renan LETHIECQ, Philippe GALY
  • System for measuring the power level of an ambient energy source
    Patent number: 10587131
    Abstract: The invention concerns a measurement unit including: an electric ambient energy recovery generator; an element of capacitive storage of the electric energy generated by the generator; an electric battery; a first branch coupling an output node of the generator to a first electrode of the capacitive storage element; a second branch coupling a first terminal of the battery to the first electrode of the capacitive storage element; and an active circuit capable of transmitting a radio event indicator signal each time the voltage across the capacitive storage element exceeds a first threshold, wherein, in operation, the capacitive storage element simultaneously receives a first charge current originating from the generator via the first branch and a second charge current originating from the battery via the second branch.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: March 10, 2020
    Assignees: Commissariat à I'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Séverin Trochut, Stéphane Monfray, Sébastien Boisseau
  • Flip flop of a digital electronic chip
    Patent number: 10585143
    Abstract: A flip flop includes a data input, a clock input, a test chain input, a test chain output, a monitoring circuit, and an alert transmission circuit. The monitoring circuit is adapted to generate an alert if the time between arrival of a data bit and a clock edge is less than a threshold. The alert transmission circuit is adapted to apply during a monitoring phase an alert level to the test chain output in the event of an alert generated by the monitoring circuit, and to apply the alert level to the test chain output when an alert level is received at the test chain input.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: March 10, 2020
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Pascal Urard, Florian Cacho, Vincent Huard, Alok Kumar Tripathi
  • Radio frequency signal attenuator and method of operation thereof
    Patent number: 10560071
    Abstract: An embodiment attenuator includes a plurality of circuits coupled in series. A respective circuit includes a first capacitor connected between an input node of the respective circuit and an output node of the respective circuit, and a second capacitor connected between the output node of the respective circuit and a reference node. The output node of the respective circuit, other than a last circuit of the plurality of circuits, is connected to the input node of a successive circuit. The attenuator further includes a plurality of selectors, in which the respective circuit is associated with a respective selector that is coupled between the output node of the respective circuit and an output node of the attenuator.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: February 11, 2020
    Assignee: STMICROELECTRONICS SA
    Inventor: Renald Boulestin
  • Method for synchronizing an active load modulation clock within a transponder, and corresponding transponder
    Patent number: 10560255
    Abstract: A transponder communicates with a reader using active load modulation. The transponder includes a digital phase locked loop (DPLL), which, in operation, generates an active load modulation (ALM) carrier clock synchronized to carrier clock of the reader. Between transmission of data frames, the DPLL is placed in a lock mode of operation in which a feedback loop of the DPLL is closed. Within a transmitted data frame having a duration, the DPLL is placed, for the duration of the transmitted data frame, in a hold mode of operation in which the feedback loop is opened. A phase of the ALM carrier clock is adjusted at least once during the duration of the transmitted data frame.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: February 11, 2020
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS RAZVOJ POLPREVODNIKOV D.O.O.
    Inventors: Maksimiljan Stiglic, Nejc Suhadolnik, Marc Houdebine
  • Electronic device with an upscaling processor and associated method
    Patent number: 10540750
    Abstract: An electronic device includes a SPAD array and readout circuitry coupled thereto. The readout circuitry generates a depth map having a first resolution, and a signal count map having a second resolution greater than the first resolution. The depth map corresponds to distance observations to an object. The signal count map corresponds to intensity observation sets of the object, with each intensity observation set including intensity observations corresponding to a respective distance observation in the depth map. An upscaling processor is coupled to the readout circuitry to calculate upscaling factors for each intensity observation set so that each distance observation has respective upscaling factors associated therewith. The depth map is then upscaled from the first resolution to the second resolution based on the respective upscaling factors.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: January 21, 2020
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED
    Inventors: Ed Hawkins, Arnaud Bourge, Chandan Siyag
  • Method for manufacture of a semiconductor wafer suitable for the manufacture of an SOI substrate, and SOI substrate wafer thus obtained
    Patent number: 10535552
    Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: January 14, 2020
    Assignee: STMicroelectronics SA
    Inventors: Didier Dutartre, Herve Jaouen
  • SUBSTRATE CONTACT FOR A TRANSISTOR, INTENDED IN PARTICULAR FOR A MATRIX-ARRAY ARRANGEMENT
    Publication number: 20200013901
    Abstract: An integrated electronic device, comprising at least one MOS transistor produced in and on an active zone of a silicon-on-insulator substrate, said at least one first transistor including a first gate region and a first substrate contact zone that is surrounded by the first gate region.
    Type: Application
    Filed: July 1, 2019
    Publication date: January 9, 2020
    Applicant: STMicroelectronics SA
    Inventors: Louise De Conti, Philippe Galy