Abstract: A photodetector including an amorphous silicon photodiode having its anode connected to a reference voltage, an initialization MOS transistor connected between the cathode of the photodiode and a first supply voltage to set the cathode to the first supply voltage during an initialization phase, and means for measuring the voltage of the photodiode cathode, including saturation means for bringing the photodiode cathode to a saturation voltage close to the reference voltage immediately before the initialization phase.

Abstract: The high-gain photodetector is formed in a semiconductor-material body which houses a PN junction and a sensitive region that is doped with rare earths, for example erbium. The PN junction forms an acceleration and gain region separate from the sensitive region. The PN junction is reverse-biased and generates an extensive depletion region accommodating the sensitive region. Thereby, the incident photon having a frequency equal to the absorption frequency of the used rare earth crosses the PN junction, which is transparent to light, can be captured by an erbium ion in the sensitive region, so as to generate a primary electron, which is accelerated towards the PN junction by the electric field present, and can, in turn, generate secondary electrons by impact, according to an avalanche process. Thereby, a single photon can give rise to a cascade of electrons, thus considerably increasing detection efficiency.

Abstract: A reading circuit for a memory includes a current detector for each bit line of the memory, a reference voltage generator, and a comparator that compares the reference voltage with the voltage of a reading terminal of the current detector. Each current detector includes a first transistor whose gate is selectively connected to the reading terminal, and whose drain-source path is in series with a respective bit line. An input of a first inverter stage is connected to the source of the first transistor, and an output thereof is connected to the gate of the first transistor. The circuit has a very short reading time based upon each of the current detectors including a first resistor between the source of the first transistor and the bit line, along with second and third transistors having their drain-source paths connected in series with the respective bit line, and along with second and third inverters connected to the respective bit line.

Abstract: A method of re-programming an array of non-volatile memory cells after an erase operation is provided where a re-program operation is executed to restore a threshold voltage of the memory cells to a higher value than a depletion verify voltage value. The method may include identifying a first value of the depletion verify voltage, executing the re-program operation using the value of the depletion verify voltage, and verifying the array of re-programmed cells for reliability in a read mode. If the outcome of the verifying step is favorable, the re-program operation is terminated as successful. Otherwise, the value of the depletion verify voltage is modified, and the re-program operation is again executed using the modified value of the depletion verify voltage as adjusted for the actual operating conditions of the memory array.

Abstract: A non-volatile memory architecture with a word-based organization includes one selection transistor per word. This selection transistor is used for the selection of the word by the source of the memory cells. In this way, the selection may be done directly by the output signals from the address decoders using low voltage. The switching of a high voltage to the gates and the drains of the memory cells is done independently of this selection. This enables the required number of high voltage switches to be reduced.

Abstract: Transistor and method of manufacturing a bipolar transistor of the double-polysilicon, heterojunction-base type, in which a semiconducting layer with SiGe heterojunction is formed by non-selective epitaxy on an active region of a substrate and an insulating region surrounding the active region. At least one stop layer is formed on the semiconducting layer above a part of the active region. A layer of polysilicon and an upper insulating layer are formed on the semiconducting layer and on a part of the stop layer, leaving an emitter window free. An emitter region is formed by epitaxy in the emitter window, resting partially on the upper insulating layer and in contact with the semiconducting layer.

Abstract: The multilevel memory device has a memory section containing cells that can be programmed with a predetermined number of levels greater than two, i.e., a multilevel array, and a memory section containing cells that can be programmed with two levels, i.e., a bilevel array. The multilevel array is used for storing high-density data, for which speed of reading is not essential, for example for storing the operation code of the system including the memory device. On the other hand, the bilevel array is used for storing data for which high speed and reliability of reading is essential, such as the BIOS of personal computers, and the data to be stored in a cache memory. The circuitry parts dedicated to programming, writing of test instructions, and all the functions necessary for the operation of the memory device, can be common to both arrays.

Abstract: A circuit system suitable for codifying NRZ type binary signals into CMI type binary signals includes a plurality of bistable means, an EXOR type logical gate, a presynchronization device and a combinatory logic device capable of creating a CMI type binary signal by codifying with an identical circuit path the “1” bits and “0” bits, sequence of bit present in the NRZ type binary signals.

Abstract: High density MOS technology power device structure, including body regions of a first conductivity type formed in a semiconductor layer of a second conductivity type, wherein the body regions include at least one plurality of substantially rectilinear and substantially parallel body stripes each joined at its ends to adjacent body stripes by junction regions, so that the at least one plurality of body stripes and the junction regions form a continuous, serpentine-shaped body region.

Abstract: Process for forming salicide on active areas of MOS transistors, each MOS transistor comprising a gate and respective source and drain regions, the source and drain regions each comprising a first lightly doped sub-region adjacent the gate and a second highly doped sub-region spaced apart from the gate. The salicide is formed selectively at least over the second highly doped sub-regions of the source and drain regions of the MOS transistors, and not over the first lightly doped sub-region.

Abstract: A code word includes a first group of data bits and includes code bits that represent a second group of data bits. One embodiment of the code word has a minimum probability of bit transitions among its bits. Another embodiment of the code word includes a parity bit. Unlike conventional codes, a code that includes such a code word can have both a high efficiency and small error propagation. Additionally, by including fewer bit transitions, a sequence of such code words causes less read noise, and thus causes fewer read errors as compared to sequences of known code words. Moreover, the code word can include a parity bit to allow improved error detection as compared to known error-detection techniques. Therefore, such a code word can significantly increase the effective write and read speeds of a disk drive.

Abstract: A receiving circuit is described for a CAN (Controlled Area Network) system with digital data transfer via a bus with parallel, redundant pulse signal transfer via two fines. The receiving circuit includes a comparator circuit assembly for differential evaluation of the two pulse signals received via the two lines, with an offset voltage being superimposed on the pulse signal received via one of the two lines prior to said differential evaluation. The comparator circuit assembly superimposes both a positive offset voltage and a negative offset voltage. A bistable multivibrator circuit is connected between the output side of the comparator circuit assembly and the output of the receiving circuit.

Abstract: A method and circuit computes a Discrete Cosine Transform in a more efficient manner for improving the computation speed, thereby reducing the computation time and allowing a higher number of digital samples to be processed. The circuit provides a microcontroller that includes a parallel accumulation multiplier for performing a first transform of the input data. A further quantization step is then performed on the transformed data. Likewise, the method includes the first transform being computed by the parallel accumulation multiplier. A further quantization step is performed on the transformed data. In this respect, the method and circuit provides good performance in terms of compression rate.

Abstract: A circuit device for performing hierarchic row decoding in semiconductor memory devices of the non-volatile type, which memory devices include an array of memory cells with column-ordered sectors, wherein each sector has a respective group of local wordlines linked to a main wordline. The circuit device includes a main wordline driver provided at each main wordline, and a local decoder provided at each local wordline. This circuit device further comprises, for each main wordline, a dedicated path connected between the main wordline and the local decoders of the associated local wordlines and connected to an external terminal arranged to receive a read/program voltage, the dedicated path enabling transfer of the read/program voltage to the local decoders.

Abstract: A noise compensating device in a discrete time control system, such as a R/W system for hard disks, including: a control loop generating a first timing signal, a signal indicative of a quantity to be controlled, and a control signal, which have a first frequency; and an open loop control line which generates a compensation signal synchronous with the control signal and includes a sensor. The sensor includes a sensing element, generating an analog signal, an acquisition stage, connected to the sensing element and generating a disturbance measure signal correlated to the analog signal and synchronous with the control signal, and a synchronization stage. The synchronization stage includes a frequency generator having an input receiving the first timing signal and a first and a second output connected to the acquisition stage and generating, respectively, a second timing signal and a third timing signal.

Abstract: A multi-carrier transmission system using orthogonal carriers with high order QAM constellations for the transmission of multiple bits per carrier and symbol. Such systems place high demands on the synchronization of the receiver with the transmitter. The maximum permitted deviation from exact synchronization is usually a small fraction of a sampling interval. A reserve carrier, the pilot carrier, which is given a fixed phase, is usually used as the reference to achieve this high accuracy. The receiver sampling clock oscillator is phase locked to the pilot carrier. It is therefore necessary to estimate the phase of the pilot carrier. Using a bandpass filter to recover the pilot carrier, regardless of the frame structure of the DMT signal, does not eliminate the influence of neighboring carriers on the pilot carrier.

Abstract: A disk drive system corrects run-out errors without substantial PES transients and without significant response time. The disk drive system includes a servo compensation system coupled to a read/write head. The servo compensation system is adapted to generate a run-out correction waveform for a track in a disk. The run-out correction waveform includes one or more sinusoidal component waveforms, each of which is defined by a phase and an amplitude. The method includes measuring an amplitude and a phase of one or more sinusoidal component waveforms for a set of specified tracks in a disk. The method also includes determining a phase and an amplitude of one or more sinusoidal component waveforms for a destination track based on a measured amplitude and a measured phase of the one or more measured sinusoidal component waveforms. The sinusoidal component waveforms for the destination track are adapted to substantially correct a run-out error in the destination track.

Abstract: The method for timing reading of a memory cell envisages supplying the memory cell (with a constant current by means of a first capacitive element, integrating said current in a time interval, and controlling the duration of the time interval in such a way as to compensate for any deviations in the current from a nominal value. In particular, a reference current is supplied to a reference cell by means of a second capacitive element; next, a first voltage present on the second capacitive element is measured; finally, the memory cell is deactivated when the first voltage is equal to a second voltage, which is constant.

Abstract: An integrated device having: a first conductive region; a second conductive region; an insulating layer arranged between the first and the second conductive region; at least one through opening extending in the insulating layer between the first and the second conductive region; and a contact structure formed in the through opening and electrically connecting the first conductive region and the second conductive region. The contact structure is formed by a conductive material layer that coats the side surface and the bottom of the through opening and surrounds an empty region which is closed at the top by the second conductive region. The conductive material layer preferably comprises a titanium layer and a titanium-nitride layer arranged on top of one another.

Abstract: Each connecting pad includes a continuous top metal layer on the top metallization level and having on its top face an area for welding a connecting wire. Also, the pad has a reinforcing structure under the welding area and includes at least one discontinuous metal layer on the immediately next lower metallization level, metal vias connecting the discontinuous metal layer to the bottom surface of the top metal layer, and an isolating cover covering the discontinuous metal layer and its discontinuities as well as the inter-via spaces between the two metallic layers.