Abstract: A circuit for splitting poles between a first stage and a second inverting voltage-amplifier stage of an electronic circuit, comprises, in series between the output of the first stage and the output of the second stage, and in that order, a first capacitor, a second capacitor and a resistor. The circuit further comprises a voltage-divider bridge which is connected between a terminal delivering a substantially constant voltage and the output of the first stage. The output of the voltage-divider bridge is linked to the common node between the first capacitor and the second capacitor, in such a way that a first resistor of the voltage-divider bridge is connected in parallel with the first capacitor.

Abstract: A sinusoidal signal multiplier circuit produces an output sinusoidal signal substantially without any DC component. This sinusoidal signal multiplier circuit includes a first multiplication cell receiving a first sinusoidal signal at a first input and a second sinusoidal signal at a second input. The first multiplication cell delivers a first output signal. The sinusoidal signal multiplier circuit also includes a second multiplication cell, identical to the first multiplication cell, that receives the second sinusoidal signal at its first input and the first sinusoidal signal at its second input, and delivers a second output signal. The sinusoidal signal multiplier circuit also includes an adder circuit to add the first output signal and the second output signal to provide from the sinusoidal signal multiplier circuit an output signal substantially without any DC component.

Abstract: A digital frequency divider includes phase control of the output signal in increments of whole or half cycles of the input frequency. Whole cycle phase control is achieved by varying (logically or physically) the tap off point of a shift register loaded with a bit pattern for appropriate division. Half cycle phase changes are achieved by a multiplexer selecting one of two signals every half cycle.

Abstract: A computer system for executing instructions having assigned guard indicators, comprises instruction supply circuitry, pipelined execution units for receiving instructions from the supply circuitry together with at least one guard indicator selected from a set of guard indicators, the execution unit including a master guard value store containing master values for the guard indicators, and circuitry for resolving the guard values in the execution pipeline and providing a signal to indicate whether the pipeline is committed to the execution of the instruction, and an emulator having watch circuitry for effecting a watch on selected instructions supplied to the execution pipeline and synchronising circuitry for correlating resolution of the guard indicator of each selected instruction with a program count for that instruction.

Abstract: An inductance device in monolithic structure is formed from a first metallization level layer of lower parallel conductive lines extending along the inductance pattern; next, on a second level, a set of vias is formed over each underlying conductive line being associated with at least two vias; and in a third metallization level, upper conductive lines interconnected to the underlying conductive lines by means of vias, the lower and upper conductive lines being shifted with respect to one another to ensure the electric continuity.

Abstract: The microstructure, of semiconductor material, includes a micromotor and an encapsulation structure. The micromotor is externally delimited by a first and a second faces, opposed to one another, and by a side delimitation trench. The encapsulation structure surrounds the micromotor and has a bottom portion facing the second face of the micromotor, and an outer lateral portion facing the side delimitation trench. An outer separation trench extends through the bottom portion of the encapsulation structure, separates a mobile region from the external side portion, and defines, together with the side delimitation trench, a labyrinthic path for contaminating particles. A sealing ring extends on the bottom portion of the encapsulation structure around an inner separation trench separating the mobile region from a fixed central region and closes a gap between the bottom portion and a mobile component connected to the mobile region of the encapsulation structure.

Abstract: Through a comparison of the values of pixels of a first candidate predictor macroblock having pixels in homologous positions to those of a reference macroblock of identical position on the frame to that of the macroblock being estimated on a reference frame of the present sequence of picture frames, a pre-established cost function is evaluated for each comparison. The best predictor is the one producing the minimum value of cost function. The comparison may even include the summing to each predictor candidate of an update vector of smaller dimensions than the macroblocks, chosen among a plurality of pre-established update vectors, for accelerating the convergence process of the comparison.

Abstract: A planar fingerprint pattern detecting array includes a large number of individual skin-distance sensing cells that are arranged in a row/column configuration. Each sensing cell includes an amplifier having an ungrounded input node and an ungrounded output node. Output-to-input negative feedback that is sensitive to the fingerprint pattern is provided for each amplifier by way of (1) a first capacitor plate that is placed vertically under the upper surface of a dielectric layer and is connected to the ungrounded amplifier input node, (2) a second capacitor plate that is placed vertically under the upper surface of the dielectric layer in close horizontal spatial relation to the first capacitor plate and is connected to the ungrounded output node, and (3) an ungrounded fingertip whose fingerprint pattern is to be detected, which ungrounded fingertip is placed on the upper surface of the dielectric layer in close vertical spatial relation with the first and second capacitor plates.

Abstract: There is disclosed a field programmable gate array that performs in the interconnect matrix selected Boolean logic functions, such as OR gates and NOR gates, normally performed in the configurable logic blocks of the FPGA. The field programmable gate array comprises: 1) a plurality of configurable logic blocks (CLBs); 2) a plurality of interconnects; 3) a plurality of interconnect switches for coupling ones of the plurality of interconnects to each other and to inputs and outputs of the plurality of configurable logic blocks; and 4) an interconnect switch controller for controlling the plurality of interconnect switches.

Abstract: A method and apparatus for reducing convergence time in a digital filter. When the digital filter is initially run, the coefficients in the digital filter are adjusted to reduce error in the output of the digital filter. When the adjusted coefficients meet a selected error level, these coefficients are stored in a memory and the digital filter filters data. The next time the digital filter is run, the stored coefficients are loaded into the digital filter and a number of iterations are run in which the coefficients are adjusted. Then, a determination is made as to whether the error level meets a threshold that may be the same as the selected error level. If the coefficients meet the threshold, the coefficients are stored in the memory and the filter is then used to filter data.

Abstract: A Flash EEPROM having negative voltage generator means for generating a negative voltage to be supplied to control gate electrodes of memory cells for erasing the memory cells. The Flash EEPROM also has first positive voltage generator means for generating a first positive voltage, independent from an external power supply of the Flash EEPROM, to be supplied to source regions of the memory cells during erasing.

Abstract: A digital-analog converter having a sigma delta cascade modulator with two outputs, particularly a third order sigma delta modulator 2+1. The digital-analog converter includes a sigma delta modulator of the type having two outputs able to supply a first and a second signal to the two outputs; a reconstruction circuit of the first and second signals able to provide a reconstructed signal; a filter able to filter the reconstructed signal; the reconstruction circuit combining the first and second signals according to the following relationship: Yout Y1*(1+Z−1)−Y2*(1−Z−1)+Y2*Z−2*(1−Z−1), where: Yout corresponds to said reconstructed signal, Y1 corresponds to said first signal, Y2 corresponds to said according to signal, Z corresponds to the Z transform.

Abstract: An electronic circuit is for optimizing or reducing switching losses in current-driven power devices and includes a switching power device connected to an electric load. The power devices has at least one control terminal arranged to receive a predetermined drive current value produced by a first current generator. The control terminal also receives an additional drive current portion produced by a second independent current generator. Advantageously, the electronic circuit includes a control circuit for controlling a switch connected between the second current generator and the control terminal of the switching power device during the turn-on and turn-off phases of the power device.

Abstract: A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the semiconductor substrate, and a plurality of memory cells in a third portion of the semiconductor substrate. A matrix mask used for selectively removing a dielectric layer from the first and third portions of the semiconductor substrate allows dielectric to remain on a floating gate of the plurality of memory cells and on the gate electrodes of the plurality of first transistors. A control gate is then formed on the floating gate, which is separated by the dielectric. Portions of the gate electrodes for the plurality of first transistors are left free so that contact is made with the transistors.

Abstract: A temperature control system and method for integrated circuits, particularly those having a plurality of channels or power devices. The temperature control system for an integrated circuit includes at least a heat generating device; a sensor element providing a signal correlated to the working conditions of said the heat generating device such as a signal proportional to the dissipated power of the heat generating device; an elaboration circuit of the signal correlated to the working conditions of the heat generating device; and a turning off circuit of said at least a heat generating device responsively to a signal of said elaboration circuit.

Abstract: The present invention relates to a potential generation circuit of charge pump type, this circuit including at least two stages formed of capacitors and of circuitry for isolating or interconnecting the capacitors, to generate an output potential by charge transfer between the stages. The circuit is driven by two control potentials oscillating between a first and a second value. The circuit includes a self-oscillating control circuit to generate control potentials, to eliminate time delays between charge and discharge phases.

Abstract: The detection of the presence of a load associated with a power MOS transistor integrated with its control circuit, using a delay determined taking into account the detection with respect to the occurrence of a turn-off control order of the power transistor, and where the filtering time is controlled with the power transistor switching time.

Abstract: The present invention relates to method to improve RF measurements accuracy on an automatic testing equipment (ATE) for IC wafers by implementing a test board de-embedding phase, wherein each wafer includes a device under test located on a wafer die plane and being contacted by probecard needles of a probecard that is coupled to a configuration board through a probe interface board (PIB), the method including the following phases: performing an automatic calibration phase of the testing equipment up to an internal plane located inside the automatic testing equipment; performing a calibration plane transfer up to a plane of the configuration board using a predetermined number of calibration standard loads realized on the wafer; performing a test boards de-embedding phase up to the wafer die plane.

Abstract: A differential amplifier may include a first stage including a first transistor and a second transistor having the same polarity and assembled to constitute a differential amplifier. The first stage may be supplied by first and second mirror current sources. The differential amplifier may further include a common mode control circuit, which may include two inputs receiving a reference voltage VCM and a common mode voltage controlling the first and second mirror current sources, respectively. The differential amplifier may further include a Miller gain stage having inputs and for a setting gain-band product. The differential amplifier may further include an unlocking circuit, inserted between the common mode voltage and the Miller gain stage inputs, to cause the Miller gain stage to conduct on circuit start-up.

Abstract: A wideband differential amplifier includes a first differential stage connected to a Miller stage allowing an open-loop gain increase. The Miller stage includes a current source and a resistive-capacitive network causing a feedback into the current source. The feedback includes a portion of a Miller stage output signal having a high frequency range to move a bias point of the current source within the high frequency range. Thus, a gain of the Miller stage significantly increases towards the bias point.